coreboot-gerrit April 2022

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Change in coreboot[master]: cpu/x86/smm: Refactor creating a stub/save state map
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63474 ) Change subject: cpu/x86/smm: Refactor creating a stub/save state map ...................................................................... cpu/x86/smm: Refactor creating a stub/save state map This code was very hard to read so rewrite in a mostly pure functional way. Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 27 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63474/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 9068435..34f2e76 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -85,65 +85,50 @@ * input : num_cpus in the system. The map will * be created from 0 to num_cpus. */ -static int smm_create_map(uintptr_t smbase, unsigned int num_cpus, +static int smm_create_map(const uintptr_t smbase, unsigned int num_cpus, const struct smm_loader_params *params) { - unsigned int i; struct rmodule smm_stub; - unsigned int ss_size = params->per_cpu_save_state_size, stub_size; - unsigned int smm_entry_offset = SMM_ENTRY_OFFSET; - unsigned int seg_count = 0, segments = 0, available; - unsigned int cpus_in_segment = 0; - unsigned int base = smbase; + + if (ARRAY_SIZE(cpus) < num_cpus) { + printk(BIOS_ERR, "%s: increase MAX_CPUS in Kconfig\n", __func__); + return 0; + } if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__); return 0; } - stub_size = rmodule_memory_size(&smm_stub); + const size_t stub_size = rmodule_memory_size(&smm_stub); /* How many CPUs can fit into one 64K segment? */ - available = 0xFFFF - smm_entry_offset - ss_size - stub_size; - if (available > 0) { - cpus_in_segment = available / ss_size; - /* minimum segments needed will always be 1 */ - segments = num_cpus / cpus_in_segment + 1; - printk(BIOS_DEBUG, - "%s: cpus allowed in one segment %d\n", __func__, cpus_in_segment); - printk(BIOS_DEBUG, - "%s: min # of segments needed %d\n", __func__, segments); - } else { - printk(BIOS_ERR, "%s: not enough space in SMM to setup all CPUs\n", __func__); - printk(BIOS_ERR, " save state & stub size need to be reduced\n"); - printk(BIOS_ERR, " or increase SMRAM size\n"); + const size_t needed_ss_size = MAX(params->real_cpu_save_state_size, stub_size); + const size_t cpus_per_segment = (SMM_CODE_SEGMENT_SIZE - SMM_ENTRY_OFFSET) / needed_ss_size; + + if (cpus_per_segment == 0) { + printk(BIOS_ERR, "%s: CPUs won't fit in segment. Broken stub or save state size\n", + __func__); return 0; } - if (ARRAY_SIZE(cpus) < num_cpus) { - printk(BIOS_ERR, - "%s: increase MAX_CPUS in Kconfig\n", __func__); - return 0; - } - - for (i = 0; i < num_cpus; i++) { + for (int i = 0; i < num_cpus; i++) { + if (i % cpus_per_segment == 0) + printk(BIOS_DEBUG, "-------------NEW CODE SEGMENT --------------\n"); printk(BIOS_DEBUG, "CPU 0x%x\n", i); - cpus[i].smbase = base; - cpus[i].entry = base + smm_entry_offset; - printk(BIOS_DEBUG, " smbase %lx entry %lx\n", cpus[i].smbase, - cpus[i].entry); - cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); + /* We copy the same stub for each CPU so they all need the same 'smbase'. */ + const size_t segment_number = i / cpus_per_segment; + cpus[i].entry = smbase - SMM_CODE_SEGMENT_SIZE * segment_number + - needed_ss_size * (i % cpus_per_segment) + SMM_ENTRY_OFFSET; + cpus[i].smbase = cpus[i].entry - SMM_ENTRY_OFFSET; + cpus[i].ss_start = + cpus[i].entry + (SMM_ENTRY_OFFSET - needed_ss_size); cpus[i].code_start = cpus[i].entry; cpus[i].code_end = cpus[i].entry + stub_size; - printk(BIOS_DEBUG, " ss_start %lx code_end %lx\n", cpus[i].ss_start, - cpus[i].code_end); + printk(BIOS_DEBUG, " Stub [0x%lx-0x%lx[\n", cpus[i].code_start, cpus[i].code_end); + printk(BIOS_DEBUG, " Save state [0x%lx-0x%lx[\n", + cpus[i].ss_start + needed_ss_size - params->real_cpu_save_state_size, + cpus[i].ss_start + needed_ss_size); cpus[i].active = 1; - base -= ss_size; - seg_count++; - if (seg_count >= cpus_in_segment) { - base -= smm_entry_offset; - seg_count = 0; - printk(BIOS_DEBUG, "-------------NEW CODE SEGMENT --------------\n"); - } } return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/63474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a455ba45a1c92533a8ecfd1aeecf34b4a63e409 Gerrit-Change-Number: 63474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86/smm_module_loader.c: Clean up printing the CPU map
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63473 ) Change subject: cpu/x86/smm_module_loader.c: Clean up printing the CPU map ...................................................................... cpu/x86/smm_module_loader.c: Clean up printing the CPU map There is no reason to do this in a separate loop. Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm_module_loader.c 1 file changed, 6 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/63473/1 diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 17c6779..9068435 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -126,38 +126,26 @@ } for (i = 0; i < num_cpus; i++) { + printk(BIOS_DEBUG, "CPU 0x%x\n", i); cpus[i].smbase = base; cpus[i].entry = base + smm_entry_offset; + printk(BIOS_DEBUG, " smbase %lx entry %lx\n", cpus[i].smbase, + cpus[i].entry); cpus[i].ss_start = cpus[i].entry + (smm_entry_offset - ss_size); cpus[i].code_start = cpus[i].entry; cpus[i].code_end = cpus[i].entry + stub_size; + printk(BIOS_DEBUG, " ss_start %lx code_end %lx\n", cpus[i].ss_start, + cpus[i].code_end); cpus[i].active = 1; base -= ss_size; seg_count++; if (seg_count >= cpus_in_segment) { base -= smm_entry_offset; seg_count = 0; + printk(BIOS_DEBUG, "-------------NEW CODE SEGMENT --------------\n"); } } - if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { - seg_count = 0; - for (i = 0; i < num_cpus; i++) { - printk(BIOS_DEBUG, "CPU 0x%x\n", i); - printk(BIOS_DEBUG, - " smbase %lx entry %lx\n", - cpus[i].smbase, cpus[i].entry); - printk(BIOS_DEBUG, - " ss_start %lx code_end %lx\n", - cpus[i].ss_start, cpus[i].code_end); - seg_count++; - if (seg_count >= cpus_in_segment) { - printk(BIOS_DEBUG, - "-------------NEW CODE SEGMENT --------------\n"); - seg_count = 0; - } - } - } return 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fe9f1004597602147aae72f4b754395b6b527cf Gerrit-Change-Number: 63473 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: ChromeOS: Add DECLARE_x_CROS_GPIOS()
by Tim Wawrzynczak (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nick Vaccaro, Kyösti Mälkki, Fred Reitberger, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58899 ) Change subject: ChromeOS: Add DECLARE_x_CROS_GPIOS() ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/58899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Gerrit-Change-Number: 58899 Gerrit-PatchSet: 18 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:17:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Allow to build romstage sources inside the bootblock
by Branden Waldner (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Martin Roth, ron minnich, Paul Menzel, Stefan Reinauer, Julius Werner, Angel Pons, Arthur Heymans, Keith Hui, Patrick Rudolph, Yu-Ping Wu, Felix Held. Branden Waldner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55068 ) Change subject: Allow to build romstage sources inside the bootblock ...................................................................... Patch Set 16: (1 comment) Patchset: PS16: I successfully tested patchset 16 on my asus p2b both with and without the kconfig set. SEPARATE_ROMSTAGE=n results in an increase in free space of 10496 bytes compared to it being enabled or build of master branch. -- To view, visit https://review.coreboot.org/c/coreboot/+/55068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Gerrit-Change-Number: 55068 Gerrit-PatchSet: 16 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)chromium.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Branden Waldner <scruffy99(a)gmail.com> Gerrit-CC: Keith Hui <buurin(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: ron minnich <rminnich(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 07 Apr 2022 20:04:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: tpm: Refactor TPM Kconfig dimensions
by Michael Niewöhner (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Stefan Ott, Felix Singer, Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Jes Klinke, Nico Huber, Sean Rhodes, Michał Żygowski, Johnny Lin, Christian Walter, Werner Zeh, Alexander Couzens, Yu-Ping Wu, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Angel Pons, Julius Werner, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63424 ) Change subject: tpm: Refactor TPM Kconfig dimensions ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63424/comment/96b9e035_093a2755 PS3, Line 22: LPC_TPM > I have no familiarity with LPC at all. […] The driver `src/drivers/pc80/tpm` is based on the TPM TIS specification, which describes this memory mapping for LPC/SPI TPM. However, only SPI TPMs connected via that specific SPI interface with CS#2 works. Any other (generic) SPI connection must use a real SPI driver. `MEMORY_MAPPED_TPM` sounds good, I guess. MM is too unclear. `MEMMAPPED_TPM` could be an option if we wanted to keep it shorter https://review.coreboot.org/c/coreboot/+/63424/comment/5e65e9cc_faa314db PS3, Line 18: // How the TPM chip is connected on the mainboard. : config CRB_TPM : config I2C_TPM : config SPI_TPM : config LPC_TPM (new) : > Julius suggested in https://review.coreboot.org/c/coreboot/+/63285 that MAINBOARD_HAS_XXX vs. […] I see, thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/63424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Gerrit-Change-Number: 63424 Gerrit-PatchSet: 5 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 19:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jes Klinke <jbk(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint/checkpatch.pl: Update to v5.18-2 lines related to max_line_...
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63439 to look at the new patch set (#2). Change subject: util/lint/checkpatch.pl: Update to v5.18-2 lines related to max_line_length ...................................................................... util/lint/checkpatch.pl: Update to v5.18-2 lines related to max_line_length Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c --- M util/lint/checkpatch.pl 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63439/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c Gerrit-Change-Number: 63439 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/lint/checkpatch.pl: Update to v5.18-2 lines related to tabsize
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63438 to look at the new patch set (#2). Change subject: util/lint/checkpatch.pl: Update to v5.18-2 lines related to tabsize ...................................................................... util/lint/checkpatch.pl: Update to v5.18-2 lines related to tabsize Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b --- M util/lint/checkpatch.pl 1 file changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/63438/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b Gerrit-Change-Number: 63438 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosity
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Martin Roth. Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63437 to look at the new patch set (#3). Change subject: util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosity ...................................................................... util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosity Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa --- M util/lint/checkpatch.pl 1 file changed, 95 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/63437/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63437 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa Gerrit-Change-Number: 63437 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell"
by Elyes Haouas (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63435 to look at the new patch set (#2). Change subject: util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell" ...................................................................... util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell" Change-Id: I55cc4255ea88723c813a04d87e4c028c64f92dbd Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/lint/checkpatch.pl 1 file changed, 47 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/63435/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55cc4255ea88723c813a04d87e4c028c64f92dbd Gerrit-Change-Number: 63435 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: Update helper function to know size of memchipinfo
by Julius Werner (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Ravi Kumar Bokka, Paul Menzel, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63026 ) Change subject: soc/qualcomm/common: Update helper function to know size of memchipinfo ...................................................................... Patch Set 9: (1 comment) File src/soc/qualcomm/common/qclib.c: https://review.coreboot.org/c/coreboot/+/63026/comment/e536b149_0553e90d PS5, Line 30: uint64_t * > hi julius, […] Fair enough... I thought blob_address was a void* already. So the cast was not unnecessary after all. Please change it back to a (void *) cast then. -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 9 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 18:17:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022