coreboot-gerrit April 2022

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 6: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63289/comment/94fecc01_9a38bda4 PS5, Line 7: Add strict flag to clock_configure() > You do not only add the flag, you also change behavior. […] We ended up removing the flag, but changing the behavior to check for exact matches all the time. The commit message has been updated to explain the reason for the change and what the behavior change is. https://review.coreboot.org/c/coreboot/+/63289/comment/8cebb4c9_e4f63e62 PS5, Line 12: > What call sites do you change, and why? Please describe the problem. Every device that calls clock_configure() (SPI, emmc, sd card, edp, etc.) will be effected by this change. File src/soc/qualcomm/common/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/558fc7b8_b60cf416 PS5, Line 104: assert(hz == clk_cfg[idx].hz) > Why assert and not log an error? This has been changed to a die() in the latest patchset. File src/soc/qualcomm/common/include/soc/clock_common.h: https://review.coreboot.org/c/coreboot/+/63289/comment/9671d103_850bfc70 PS5, Line 151: strict=1 > strict=true This does not apply anymore. https://review.coreboot.org/c/coreboot/+/63289/comment/42bb109d_90f2c7ab PS5, Line 158: strict > Maybe exact_match? This does not apply anymore in the latest patchset. File src/soc/qualcomm/sc7180/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/1ab2c715_f3a198f8 PS4, Line 218: &mdss_clk_cfg, 0, 0, false); > Sure that works too, just make sure it die()s or something when running over the end of the array. Done File src/soc/qualcomm/sc7180/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/23c45f63_d6e6c47f PS5, Line 120: clock_configure > Instead of having one more argument in the signature, I’d prefer a new function […] This does not apply anymore in the latest patchset. We got rid of the strict parameter so there's only one version of the function. -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 17:23:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63289 to look at the new patch set (#6). Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... soc/qualcomm/common: Make clock_configure() check for exact matches Previously, clock_configure() will configure the clocks to round up to the next highest frequency bin. This seems non-intuitive. Changing the logic to find an exact frequency match and will halt booting if not found. Recently fixed a bug in CB:63311, where the clock was being set incorrectly for emmc and was able to find it because of this stricter check. BUG=b:198627043 BRANCH=None TEST=build herobrine image and try to set SPI frequency to number not supported. Ensure device doesn't boot. Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7280/clock.c 4 files changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63289/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 6 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: register generic LPC resources
by Michael Niewöhner (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Paul Menzel, Michał Kopeć, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63341 ) Change subject: soc/intel/common: register generic LPC resources ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/lpc/lpc.c: https://review.coreboot.org/c/coreboot/+/63341/comment/bd41bec3_557ef71c PS2, Line 54: > nit: drop blank line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f45b38498390016f841ab1d70c8438496dc857e Gerrit-Change-Number: 63341 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 17:15:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: register generic LPC resources
by Michael Niewöhner (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Felix Singer, Nico Huber, Michał Żygowski, Paul Menzel, Michał Kopeć, Tim Wawrzynczak, Angel Pons, Patrick Rudolph. Hello Felix Singer, build bot (Jenkins), Nico Huber, Michał Żygowski, Paul Menzel, Michał Kopeć, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63341 to look at the new patch set (#3). Change subject: soc/intel/common: register generic LPC resources ...................................................................... soc/intel/common: register generic LPC resources Register the generic LPC memory/IO ranges with the resource allocator. TEST: set ranges and check the coreboot log Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I9f45b38498390016f841ab1d70c8438496dc857e --- M src/soc/intel/common/block/lpc/lpc.c 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63341/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f45b38498390016f841ab1d70c8438496dc857e Gerrit-Change-Number: 63341 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/common/block: Add gpmr common driver
by Wonkyu Kim (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63170 ) Change subject: intel/common/block: Add gpmr common driver ...................................................................... Patch Set 10: (1 comment) Patchset: PS9: > Will update as GPMR driver and use GPMR api. Plan to split patches as 3. And this patch will be updated as #1. -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 17:14:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/block: Add gpmr common driver
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63170 ) Change subject: intel/common/block: Add gpmr common driver ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145781): https://review.coreboot.org/c/coreboot/+/63170/comment/52ac191c_83e78ab8 PS10, Line 19: #define GPMR_TCOEN (1 << 1) please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 17:14:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: use gpmr api in common drivers
by Wonkyu Kim (Code Review) 07 Apr '22

07 Apr '22

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63471 ) Change subject: soc/intel/common: use gpmr api in common drivers ...................................................................... soc/intel/common: use gpmr api in common drivers Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/lpc/Kconfig M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/common/pch/lockdown/lockdown.c 6 files changed, 23 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/63471/1 diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5a76df3..8bd9485 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -11,8 +11,8 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpmr.h> #include <lib.h> #include <soc/pci_devs.h> #include <spi_flash.h> @@ -325,7 +325,7 @@ #endif /* Configure Source decode for Extended BIOS Region */ - if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, + if (enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_psf_destination_id()) == CB_ERR) return; diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index d76620a..2fac5ff 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -12,9 +12,9 @@ By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection. -config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI +config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR bool - depends on SOC_INTEL_COMMON_BLOCK_DMI + depends on SOC_INTEL_COMMON_BLOCK_GPMR help - Mirror LPC registers for IO/MMIO to their corresponding DMI registers. + Mirror LPC registers for IO/MMIO to their corresponding GPMR registers. Required for platforms starting from SPT. diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 1393714..d57f1bc 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -7,6 +7,7 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/gpmr.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> @@ -24,8 +25,8 @@ reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCIOE, io_enables); return io_enables; } @@ -42,8 +43,8 @@ reg_io_ranges = lpc_get_fixed_io_decode() & ~mask; io_ranges |= reg_io_ranges & mask; pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCIOD, io_ranges); return io_ranges; } @@ -112,8 +113,8 @@ lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num); pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCLGIR1 + lgir_reg_num * 4, lgir); printk(BIOS_DEBUG, "LPC: Opened IO window LGIR%d: base %llx size %x\n", @@ -147,8 +148,8 @@ lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN; pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCGMR, lgmr); } /* @@ -248,8 +249,8 @@ /* Set in PCI generic decode range registers */ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCLGIR1 + i * 4, gen_io_dec[i]); } } diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 518541b..1ca8842 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include <intelblocks/gpmr.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -16,10 +17,6 @@ #include <soc/pm.h> #include <soc/smbus.h> -#define PCR_DMI_TCOBASE 0x2778 -/* Enable TCO I/O range decode. */ -#define TCOEN (1 << 1) - /* SMBUS TCO base address. */ #define TCOBASE 0x50 #define TCOCTL 0x54 @@ -122,10 +119,8 @@ /* Enable TCO in SMBUS */ pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN); - /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); + /* Program TCO Base Address */ + gpmr_write32(GPMR_TCOBASE, tcobase | GPMR_TCOEN); } /* diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 6ccf79d..7951298 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -33,7 +33,7 @@ select SOC_INTEL_COMMON_BLOCK_GPMR select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPC - select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..7f7b8eb 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -2,10 +2,10 @@ #include <bootstate.h> #include <intelblocks/cfg.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> +#include <intelblocks/gpmr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> @@ -27,23 +27,8 @@ static void dmi_lockdown_cfg(void) { - /* - * GCS reg of DMI - * - * When set, prevents GCS.BBS from being changed - * GCS.BBS: (Boot BIOS Strap) This field determines the destination - * of accesses to the BIOS memory range. - * Bits Description - * "0b": SPI - * "1b": LPC/eSPI - */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); - - /* - * Set Secure Register Lock (SRL) bit in DMI control register to lock - * DMI configuration. - */ - pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); + gpmr_or32(GPMR_GCS, GPMR_GCS_BILD); + gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); } static void fast_spi_lockdown_cfg(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/63471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Gerrit-Change-Number: 63471 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/block: Add gpmr common driver
by Wonkyu Kim (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. Hello build bot (Jenkins), Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63170 to look at the new patch set (#10). Change subject: intel/common/block: Add gpmr common driver ...................................................................... intel/common/block: Add gpmr common driver Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b --- A src/soc/intel/common/block/gpmr/Kconfig A src/soc/intel/common/block/gpmr/Makefile.inc A src/soc/intel/common/block/gpmr/gpmr.c A src/soc/intel/common/block/include/intelblocks/gpmr.h A src/soc/intel/common/block/include/intelblocks/pcr_gpmr.h M src/soc/intel/common/pch/Kconfig 6 files changed, 139 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/63170/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Gerrit-Change-Number: 63170 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63463 ) Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 16:56:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
by Angel Pons (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63457 ) Change subject: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 Gerrit-Change-Number: 63457 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 16:55:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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