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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 )
Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/stout/bootmode.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145775):
https://review.coreboot.org/c/coreboot/+/59011/comment/551dfaac_4bcb0cbe
PS8, Line 44: printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n",
space required after that ',' (ctx:VxV)
File src/mainboard/intel/kblrvp/bootmode.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145775):
https://review.coreboot.org/c/coreboot/+/59011/comment/483505f3_dd713321
PS8, Line 21: if (google_chromeec_get_switches() &
suspect code indent for conditional statements (16, 16)
--
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Gerrit-Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f
Gerrit-Change-Number: 59011
Gerrit-PatchSet: 8
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63304 )
Change subject: soc/intel/alderlake: Hook up PAVP to Kconfig
......................................................................
soc/intel/alderlake: Hook up PAVP to Kconfig
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for
multimedia content) to Kconfig.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63304
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Felix Singer: Looks good to me, approved
Angel Pons: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd41480..723ad92 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -406,6 +406,7 @@
/* Check if IGD is present and fill Graphics init param accordingly */
s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
s_cfg->LidStatus = CONFIG(RUN_FSP_GOP);
+ s_cfg->PavpEnable = CONFIG(PAVP);
}
static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
--
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Gerrit-Change-Id: I5a364a9781642eb366e5e502a4ee69008c19bcd6
Gerrit-Change-Number: 63304
Gerrit-PatchSet: 4
Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
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Gerrit-MessageType: merged
Attention is currently required from: Shon Wang.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63441 )
Change subject: mb/google/brya/var/vell: camera LED flicker problem
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
this is failing because:
File src/mainboard/google/brya/variants/vell/overridetree.cb has one or more executable bits set in the file permissions.
--
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Gerrit-Branch: master
Gerrit-Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
Gerrit-Change-Number: 63441
Gerrit-PatchSet: 1
Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63303 )
Change subject: soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
......................................................................
soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree
The FSP needs to program VrPowerDeliverDesign configuration per
platform according to the platform capabilities to avoid incorrect
electrial/power parameters. This value is an enum of the available
power delivery segments that are defined in the Platform Design
Guide.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I74859e6735e59a15084a9e690b43f68341862833
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63303
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a69e645..2dae9cd 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -441,6 +441,13 @@
uint8_t dmi_power_optimize_disable;
/*
+ * Used to communicate the power delivery design capability of the board. This
+ * value is an enum of the available power delivery segments that are defined in
+ * the Platform Design Guide.
+ */
+ uint8_t vr_power_delivery_design;
+
+ /*
* Enable(1)/Disable(0) CPU Replacement check.
* Default 0. Setting this to 1 to check CPU replacement.
*/
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd2c0be..bd41480 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -748,6 +748,8 @@
}
s_cfg->C1StateAutoDemotion = !config->disable_c1_state_auto_demotion;
+
+ s_cfg->VrPowerDeliveryDesign = config->vr_power_delivery_design;
}
static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
--
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Gerrit-Change-Number: 63303
Gerrit-PatchSet: 4
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Attention is currently required from: Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Kyösti Mälkki, Fred Reitberger, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Nick Vaccaro, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59011
to look at the new patch set (#8).
Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
[WIP] mb/google,intel: Split chromeos.c files
Move all the low-level GPIO support in bootmode.c files and build
them for all stages. Keep ChromeOS related ACPI and lbtable support
in chromeos.c files and build them only for ramstage.
Change-Id: I71a02c5fa1b256316b86b673660bf22dfd284f7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/mainboard/amd/chausie/Makefile.inc
M src/mainboard/amd/majolica/Makefile.inc
M src/mainboard/emulation/qemu-q35/chromeos.c
M src/mainboard/google/asurada/Makefile.inc
A src/mainboard/google/asurada/bootmode.c
M src/mainboard/google/asurada/chromeos.c
M src/mainboard/google/auron/Makefile.inc
A src/mainboard/google/auron/bootmode.c
M src/mainboard/google/auron/chromeos.c
M src/mainboard/google/beltino/Makefile.inc
A src/mainboard/google/beltino/bootmode.c
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/brya/Makefile.inc
A src/mainboard/google/brya/bootmode.c
M src/mainboard/google/brya/chromeos.c
M src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/brask/chromeos.c
M src/mainboard/google/brya/variants/baseboard/brask/gpio.c
M src/mainboard/google/brya/variants/baseboard/brya/Makefile.inc
A src/mainboard/google/brya/variants/baseboard/brya/chromeos.c
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
M src/mainboard/google/brya/variants/kinox/gpio.c
M src/mainboard/google/butterfly/Makefile.inc
A src/mainboard/google/butterfly/bootmode.c
M src/mainboard/google/butterfly/chromeos.c
M src/mainboard/google/cherry/Makefile.inc
A src/mainboard/google/cherry/bootmode.c
M src/mainboard/google/cherry/chromeos.c
M src/mainboard/google/corsola/Makefile.inc
A src/mainboard/google/corsola/bootmode.c
M src/mainboard/google/corsola/chromeos.c
M src/mainboard/google/cyan/Makefile.inc
A src/mainboard/google/cyan/bootmode.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/daisy/Makefile.inc
A src/mainboard/google/daisy/bootmode.c
M src/mainboard/google/daisy/chromeos.c
M src/mainboard/google/dedede/Makefile.inc
A src/mainboard/google/dedede/bootmode.c
M src/mainboard/google/dedede/chromeos.c
M src/mainboard/google/dedede/variants/baseboard/Makefile.inc
A src/mainboard/google/dedede/variants/baseboard/chromeos.c
M src/mainboard/google/dedede/variants/baseboard/gpio.c
M src/mainboard/google/eve/Makefile.inc
A src/mainboard/google/eve/bootmode.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/Makefile.inc
A src/mainboard/google/fizz/bootmode.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/fizz/variants/baseboard/Makefile.inc
A src/mainboard/google/fizz/variants/baseboard/chromeos.c
M src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/foster/Makefile.inc
A src/mainboard/google/foster/bootmode.c
M src/mainboard/google/foster/chromeos.c
M src/mainboard/google/gale/Makefile.inc
A src/mainboard/google/gale/bootmode.c
M src/mainboard/google/gale/chromeos.c
M src/mainboard/google/glados/Makefile.inc
A src/mainboard/google/glados/bootmode.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/gru/Makefile.inc
A src/mainboard/google/gru/bootmode.c
M src/mainboard/google/gru/chromeos.c
M src/mainboard/google/guybrush/Makefile.inc
M src/mainboard/google/guybrush/chromeos.c
M src/mainboard/google/hatch/Makefile.inc
A src/mainboard/google/hatch/bootmode.c
M src/mainboard/google/hatch/chromeos.c
M src/mainboard/google/hatch/variants/baseboard/Makefile.inc
A src/mainboard/google/hatch/variants/baseboard/chromeos.c
M src/mainboard/google/hatch/variants/baseboard/gpio.c
M src/mainboard/google/herobrine/Makefile.inc
A src/mainboard/google/herobrine/bootmode.c
M src/mainboard/google/herobrine/chromeos.c
M src/mainboard/google/jecht/Makefile.inc
A src/mainboard/google/jecht/bootmode.c
M src/mainboard/google/jecht/chromeos.c
M src/mainboard/google/kahlee/Makefile.inc
A src/mainboard/google/kahlee/bootmode.c
M src/mainboard/google/kahlee/chromeos.c
M src/mainboard/google/kukui/Makefile.inc
A src/mainboard/google/kukui/bootmode.c
M src/mainboard/google/kukui/chromeos.c
M src/mainboard/google/link/Makefile.inc
A src/mainboard/google/link/bootmode.c
M src/mainboard/google/link/chromeos.c
M src/mainboard/google/mistral/Makefile.inc
R src/mainboard/google/mistral/bootmode.c
M src/mainboard/google/nyan/Makefile.inc
A src/mainboard/google/nyan/bootmode.c
M src/mainboard/google/nyan/chromeos.c
M src/mainboard/google/nyan_big/Makefile.inc
A src/mainboard/google/nyan_big/bootmode.c
M src/mainboard/google/nyan_big/chromeos.c
M src/mainboard/google/nyan_blaze/Makefile.inc
A src/mainboard/google/nyan_blaze/bootmode.c
M src/mainboard/google/nyan_blaze/chromeos.c
M src/mainboard/google/oak/Makefile.inc
A src/mainboard/google/oak/bootmode.c
M src/mainboard/google/oak/chromeos.c
M src/mainboard/google/octopus/Makefile.inc
A src/mainboard/google/octopus/bootmode.c
M src/mainboard/google/octopus/chromeos.c
M src/mainboard/google/octopus/variants/baseboard/Makefile.inc
A src/mainboard/google/octopus/variants/baseboard/chromeos.c
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/parrot/Makefile.inc
A src/mainboard/google/parrot/bootmode.c
M src/mainboard/google/parrot/chromeos.c
M src/mainboard/google/peach_pit/Makefile.inc
A src/mainboard/google/peach_pit/bootmode.c
M src/mainboard/google/peach_pit/chromeos.c
M src/mainboard/google/poppy/Makefile.inc
A src/mainboard/google/poppy/bootmode.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/poppy/variants/baseboard/Makefile.inc
A src/mainboard/google/poppy/variants/baseboard/chromeos.c
M src/mainboard/google/poppy/variants/baseboard/gpio.c
M src/mainboard/google/rambi/Makefile.inc
A src/mainboard/google/rambi/bootmode.c
M src/mainboard/google/rambi/chromeos.c
M src/mainboard/google/reef/Makefile.inc
A src/mainboard/google/reef/bootmode.c
M src/mainboard/google/reef/chromeos.c
M src/mainboard/google/reef/variants/baseboard/Makefile.inc
A src/mainboard/google/reef/variants/baseboard/chromeos.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/coral/Makefile.inc
A src/mainboard/google/reef/variants/coral/chromeos.c
M src/mainboard/google/reef/variants/coral/gpio.c
M src/mainboard/google/slippy/Makefile.inc
A src/mainboard/google/slippy/bootmode.c
M src/mainboard/google/slippy/chromeos.c
M src/mainboard/google/smaug/Makefile.inc
A src/mainboard/google/smaug/bootmode.c
M src/mainboard/google/smaug/chromeos.c
M src/mainboard/google/storm/Makefile.inc
A src/mainboard/google/storm/bootmode.c
M src/mainboard/google/storm/chromeos.c
M src/mainboard/google/stout/Makefile.inc
A src/mainboard/google/stout/bootmode.c
M src/mainboard/google/stout/chromeos.c
M src/mainboard/google/trogdor/Makefile.inc
A src/mainboard/google/trogdor/bootmode.c
M src/mainboard/google/trogdor/chromeos.c
M src/mainboard/google/veyron/Makefile.inc
A src/mainboard/google/veyron/bootmode.c
M src/mainboard/google/veyron/chromeos.c
M src/mainboard/google/veyron_mickey/Makefile.inc
M src/mainboard/google/veyron_mickey/board.h
A src/mainboard/google/veyron_mickey/bootmode.c
M src/mainboard/google/veyron_mickey/chromeos.c
M src/mainboard/google/veyron_rialto/Makefile.inc
A src/mainboard/google/veyron_rialto/bootmode.c
M src/mainboard/google/veyron_rialto/chromeos.c
M src/mainboard/google/volteer/Makefile.inc
A src/mainboard/google/volteer/bootmode.c
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/volteer/variants/baseboard/Makefile.inc
A src/mainboard/google/volteer/variants/baseboard/chromeos.c
M src/mainboard/google/volteer/variants/baseboard/gpio.c
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/bootmode.c
M src/mainboard/google/zork/chromeos.c
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/bootmode.c
M src/mainboard/intel/adlrvp/chromeos.c
M src/mainboard/intel/adlrvp/gpio.c
M src/mainboard/intel/adlrvp/gpio_m.c
M src/mainboard/intel/adlrvp/gpio_n.c
M src/mainboard/intel/baskingridge/Makefile.inc
A src/mainboard/intel/baskingridge/bootmode.c
M src/mainboard/intel/baskingridge/chromeos.c
M src/mainboard/intel/coffeelake_rvp/Makefile.inc
A src/mainboard/intel/coffeelake_rvp/bootmode.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/Makefile.inc
A src/mainboard/intel/coffeelake_rvp/variants/baseboard/chromeos.c
M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/emeraldlake2/Makefile.inc
A src/mainboard/intel/emeraldlake2/bootmode.c
M src/mainboard/intel/emeraldlake2/chromeos.c
M src/mainboard/intel/glkrvp/Makefile.inc
A src/mainboard/intel/glkrvp/bootmode.c
M src/mainboard/intel/glkrvp/chromeos.c
M src/mainboard/intel/glkrvp/variants/baseboard/Makefile.inc
A src/mainboard/intel/glkrvp/variants/baseboard/chromeos.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/bootmode.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/icelake_rvp/variants/icl_u/Makefile.inc
A src/mainboard/intel/icelake_rvp/variants/icl_u/chromeos.c
M src/mainboard/intel/icelake_rvp/variants/icl_u/gpio.c
M src/mainboard/intel/icelake_rvp/variants/icl_y/Makefile.inc
A src/mainboard/intel/icelake_rvp/variants/icl_y/chromeos.c
M src/mainboard/intel/icelake_rvp/variants/icl_y/gpio.c
M src/mainboard/intel/jasperlake_rvp/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/bootmode.c
M src/mainboard/intel/jasperlake_rvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/Makefile.inc
A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/chromeos.c
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c
M src/mainboard/intel/kblrvp/Makefile.inc
A src/mainboard/intel/kblrvp/bootmode.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/Makefile.inc
A src/mainboard/intel/kunimitsu/bootmode.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/shadowmountain/Makefile.inc
A src/mainboard/intel/shadowmountain/bootmode.c
M src/mainboard/intel/shadowmountain/chromeos.c
M src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
A src/mainboard/intel/shadowmountain/variants/baseboard/chromeos.c
M src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
M src/mainboard/intel/strago/Makefile.inc
A src/mainboard/intel/strago/bootmode.c
M src/mainboard/intel/strago/chromeos.c
M src/mainboard/intel/tglrvp/Makefile.inc
A src/mainboard/intel/tglrvp/bootmode.c
M src/mainboard/intel/tglrvp/chromeos.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
A src/mainboard/intel/tglrvp/variants/tglrvp_up3/chromeos.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/Makefile.inc
A src/mainboard/intel/tglrvp/variants/tglrvp_up4/chromeos.c
M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c
M src/mainboard/intel/wtm2/Makefile.inc
A src/mainboard/intel/wtm2/bootmode.c
M src/mainboard/intel/wtm2/chromeos.c
M src/mainboard/samsung/lumpy/Makefile.inc
A src/mainboard/samsung/lumpy/bootmode.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/stumpy/Makefile.inc
A src/mainboard/samsung/stumpy/bootmode.c
M src/mainboard/samsung/stumpy/chromeos.c
238 files changed, 1,957 insertions(+), 1,624 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59011/8
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Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: mb/google,samsung: Drop init_bootmode_straps()
......................................................................
mb/google,samsung: Drop init_bootmode_straps()
Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
M src/include/bootmode.h
M src/mainboard/google/beltino/chromeos.c
M src/mainboard/google/jecht/chromeos.c
D src/mainboard/google/jecht/romstage.c
M src/mainboard/samsung/lumpy/chromeos.c
M src/mainboard/samsung/lumpy/early_init.c
M src/mainboard/samsung/stumpy/chromeos.c
M src/mainboard/samsung/stumpy/early_init.c
M src/northbridge/intel/sandybridge/romstage.c
M src/soc/intel/broadwell/pch/Makefile.inc
10 files changed, 9 insertions(+), 173 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/59008/4
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Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63180 )
Change subject: payloads/tianocore: Don't declare tools directory twice
......................................................................
Patch Set 3: Code-Review+2
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Change subject: amdfwtool: Add a function to extract firmwares
......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21:
It might be worth integrating these changes with CB:62795. I think that might end up being a little bit cleaner.
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Change subject: mb/prodrive/atlas: Configure eSPI IO decode range for EC
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63465/comment/f34685b7_3630a600
PS2, Line 7: range
nit: plural `ranges`
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Change subject: mb/prodrive/atlas: Update kconfig
......................................................................
Patch Set 2:
(4 comments)
File src/mainboard/prodrive/atlas/Kconfig:
https://review.coreboot.org/c/coreboot/+/63464/comment/97574fdb_2db43439
PS2, Line 3: select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR
This was removed in CB:63339
https://review.coreboot.org/c/coreboot/+/63464/comment/96d466c8_f766bcd5
PS2, Line 5: select DRIVERS_I2C_GENERIC
: select DRIVERS_INTEL_DPTF
: select DRIVERS_SPI_ACPI
: select DRIVERS_USB_ACPI
These options enable various devicetree chip drivers, but just selecting them isn't really useful. It would make more sense to select these in the same commit that updates the devicetree.
https://review.coreboot.org/c/coreboot/+/63464/comment/a3ddd6db_146fb76d
PS2, Line 9: select DRIVERS_UART_8250IO
Why is this needed? AFAIK, the SerialIO UARTs are configured to use MMIO (INTEL_LPSS_UART_FOR_CONSOLE selects DRIVERS_UART_8250MEM_32).
https://review.coreboot.org/c/coreboot/+/63464/comment/6ab02271_d6dd6c2b
PS2, Line 17:
: config IGNORE_IASL_MISSING_DEPENDENCY
: def_bool y
Why is this needed?
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