coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
by Tim Wawrzynczak (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63460 ) Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63460/comment/43e0b4f9_fe52a8ca PS2, Line 9: 6030603 `630603` -- To view, visit https://review.coreboot.org/c/coreboot/+/63460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Gerrit-Change-Number: 63460 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:28:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S
by Tim Wawrzynczak (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63458 ) Change subject: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Gerrit-Change-Number: 63458 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:24:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Introduce PCH-S symbol
by Tim Wawrzynczak (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63455 ) Change subject: soc/intel/alderlake: Introduce PCH-S symbol ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > What about MAX_PCH_ROOT_PORTS, etc. […] NM I see 63457 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/63455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47676723747458b8b7fe726e900843c198901bda Gerrit-Change-Number: 63455 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:23:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Tim Wawrzynczak (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63456 ) Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Have you boot tested this yet? I am a little surprised that ADL-S supports 2.3, as ADL-P is still on 2.2. -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:23:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Introduce PCH-S symbol
by Tim Wawrzynczak (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63455 ) Change subject: soc/intel/alderlake: Introduce PCH-S symbol ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: What about MAX_PCH_ROOT_PORTS, etc. ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47676723747458b8b7fe726e900843c198901bda Gerrit-Change-Number: 63455 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 15:19:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add GPIO definitions for PCH-S
by Michał Kopeć (Code Review) 07 Apr '22

07 Apr '22

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63467 ) Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S ...................................................................... soc/intel/alderlake: add GPIO definitions for PCH-S Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles the split. Based on: - Alderlake-S FSP - slimbootloader sources - Linux alderlake-pinctrl driver Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/acpi/gpio.asl M src/soc/intel/alderlake/fsp_params.c A src/soc/intel/alderlake/gpio_pch_s.c M src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/romstage/fsp_params.c 9 files changed, 1,150 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63467/1 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index a03c42a..825cfd5 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -14,12 +14,10 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-y += gpio.c bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c romstage-y += espi.c -romstage-y += gpio.c romstage-y += meminit.c romstage-y += pcie_rp.c romstage-y += reset.c @@ -33,7 +31,6 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c -ramstage-y += gpio.c ramstage-y += lockdown.c ramstage-y += me.c ramstage-y += p2sb.c @@ -48,16 +45,27 @@ ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c -verstage-y += gpio.c - smm-y += elog.c -smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c smm-y += xhci.c +ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) +bootblock-y += gpio_pch_s.c +romstage-y += gpio_pch_s.c +ramstage-y += gpio_pch_s.c +smm-y += gpio_pch_s.c +verstage-y += gpio_pch_s.c +else +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +smm-y += gpio.c +verstage-y += gpio.c +endif + CPPFLAGS_common += -I$(src)/soc/intel/alderlake CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include diff --git a/src/soc/intel/alderlake/acpi/gpio.asl b/src/soc/intel/alderlake/acpi/gpio.asl index 376afab..d273625 100644 --- a/src/soc/intel/alderlake/acpi/gpio.asl +++ b/src/soc/intel/alderlake/acpi/gpio.asl @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <intelblocks/gpio.h> -#include <soc/gpio_defs.h> +#include <soc/gpio.h> #include <soc/intel/common/acpi/gpio.asl> #include <soc/intel/common/block/acpi/acpi/gpio_op.asl> #include <soc/irq.h> diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd2c0be..a3a76a37 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -18,7 +18,7 @@ #include <intelpch/lockdown.h> #include <intelblocks/tcss.h> #include <soc/cpu.h> -#include <soc/gpio_soc_defs.h> +#include <soc/gpio.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> #include <soc/pcie.h> diff --git a/src/soc/intel/alderlake/gpio_pch_s.c b/src/soc/intel/alderlake/gpio_pch_s.c new file mode 100644 index 0000000..c77df30 --- /dev/null +++ b/src/soc/intel/alderlake/gpio_pch_s.c @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/gpio.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <soc/pmc.h> + +#define DEFAULT_VW_BASE 0x10 + +/* + * This file is created based on Intel Alder Lake Processor PCH-S Datasheet + */ + +static const struct reset_mapping rst_map_gpp[] = { + { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, + { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, + { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, +}; +static const struct reset_mapping rst_map_gpd[] = { + { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, + { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, + { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, + { .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 }, +}; + +/* + * The GPIO pinctrl driver for Alder Lake on Linux expects 32 GPIOs per pad + * group, regardless of whether or not there is a physical pad for each + * exposed GPIO number. + * + * This results in the OS having a sparse GPIO map, and devices that need + * to export an ACPI GPIO must use the OS expected number. + * + * Not all pins are usable as GPIO and those groups do not have a pad base. + */ +static const struct pad_group adl_community0_groups[] = { + INTEL_GPP_BASE(GPP_I0, GPP_I0, GPP_GSPI1_CLK_LOOPBK, 0), /* GPP_I */ + INTEL_GPP_BASE(GPP_I0, GPP_R0, GPP_GSPI2_CLK_LOOPBK, 32), /* GPP_R */ + INTEL_GPP_BASE(GPP_I0, GPP_J0, GPP_J11, 64), /* GPP_J */ + INTEL_GPP_BASE(GPP_I0, GPP_VGPIO_0, GPP_VGPIO_37, 96), /* vGPIO */ + INTEL_GPP_BASE(GPP_I0, GPP_VGPIO_USB_0, GPP_VGPIO_USB_11, 128), /* vGPIO_0 */ +}; + +static const struct vw_entries adl_community0_vw[] = { + {GPP_I0, GPP_I14}, + {GPP_R0, GPP_R19}, + {GPP_J0, GPP_J9}, +}; + +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_B23, 160), /* GPP_B */ + INTEL_GPP_BASE(GPP_B0, GPP_G0, GPP_G7, 192), /* GPP_G */ + INTEL_GPP_BASE(GPP_B0, GPP_H0, GPP_H23, 224), /* GPP_H */ +}; + +static const struct vw_entries adl_community1_vw[] = { + {GPP_B0, GPP_B23}, + {GPP_G0, GPP_G7}, + {GPP_H0, GPP_H23}, +}; + +/* This community is not visible to the OS */ +static const struct pad_group adl_community2_groups[] = { + INTEL_GPP(GPD0, GPD0, GPD_DRAM_RESETB), /* GPD */ +}; + +static const struct pad_group adl_community3_groups[] = { + INTEL_GPP(GPP_SPI0_IO_2, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK), /* SPI0 */ + INTEL_GPP_BASE(GPP_SPI0_IO_2, GPP_A0, GPP_ESPI_CLK_LOOPBK, 256), /* GPP_A */ + INTEL_GPP_BASE(GPP_SPI0_IO_2, GPP_C0, GPP_C23, 288), /* GPP_C */ +}; + +static const struct pad_group adl_community4_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 320), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_E0, GPP_SPI1_THC0_CLK_LOOPBK, 352), /* GPP_E */ + INTEL_GPP_BASE(GPP_S0, GPP_K0, GPP_MLK_RSTB, 384), /* GPP_K */ + INTEL_GPP_BASE(GPP_S0, GPP_F0, GPP_F23, 416), /* GPP_F */ +}; + +static const struct vw_entries adl_community4_vw[] = { + {GPP_E0, GPP_E21}, + {GPP_K0, GPP_K11}, + {GPP_F0, GPP_F23}, +}; + +static const struct pad_group adl_community5_groups[] = { + INTEL_GPP_BASE(GPP_D0, GPP_D0, GPP_GSPI3_THC1_CLK_LOOPBK, 448), /* GPP_D */ + INTEL_GPP(GPP_D0, GPP_JTAG_TDO, GPP_CPU_TRSTB), /* JTAG */ +}; + +static const struct pad_community adl_communities[] = { + [COMM_0] = { /* GPP I, R, J, vGPIO. vGPIO_0 */ + .port = PID_GPIOCOM0, + .cpu_port = PID_CPU_GPIOCOM0, + .first_pad = GPIO_COM0_START, + .last_pad = GPIO_COM0_END, + .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_IRJ", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), + .groups = adl_community0_groups, + .num_groups = ARRAY_SIZE(adl_community0_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community0_vw, + .num_vw_entries = ARRAY_SIZE(adl_community0_vw), + }, + [COMM_1] = { /* GPP B, G, H */ + .port = PID_GPIOCOM1, + .cpu_port = PID_CPU_GPIOCOM1, + .first_pad = GPIO_COM1_START, + .last_pad = GPIO_COM1_END, + .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_BGH", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), + .groups = adl_community1_groups, + .num_groups = ARRAY_SIZE(adl_community1_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community1_vw, + .num_vw_entries = ARRAY_SIZE(adl_community1_vw), + }, + [COMM_2] = { /* GPD */ + .port = PID_GPIOCOM2, + .first_pad = GPIO_COM2_START, + .last_pad = GPIO_COM2_END, + .num_gpi_regs = NUM_GPIO_COM2_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPD", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_gpd, + .num_reset_vals = ARRAY_SIZE(rst_map_gpd), + .groups = adl_community2_groups, + .num_groups = ARRAY_SIZE(adl_community2_groups), + }, + [COMM_3] = { /* SPI0, GPP A, C */ + .port = PID_GPIOCOM3, + .cpu_port = PID_CPU_GPIOCOM3, + .first_pad = GPIO_COM3_START, + .last_pad = GPIO_COM3_END, + .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SPI0AC", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), + .groups = adl_community3_groups, + .num_groups = ARRAY_SIZE(adl_community3_groups), + }, + [COMM_4] = { /* GPP S, E, K, F */ + .port = PID_GPIOCOM4, + .cpu_port = PID_CPU_GPIOCOM4, + .first_pad = GPIO_COM4_START, + .last_pad = GPIO_COM4_END, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_SEKF", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), + .groups = adl_community4_groups, + .num_groups = ARRAY_SIZE(adl_community4_groups), + .vw_base = DEFAULT_VW_BASE, + .vw_entries = adl_community4_vw, + .num_vw_entries = ARRAY_SIZE(adl_community4_vw), + }, + [COMM_5] = { /* GPP D, JTAG */ + .port = PID_GPIOCOM5, + .cpu_port = PID_CPU_GPIOCOM5, + .first_pad = GPIO_COM5_START, + .last_pad = GPIO_COM5_END, + .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPP_D", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map_gpp, + .num_reset_vals = ARRAY_SIZE(rst_map_gpp), + .groups = adl_community5_groups, + .num_groups = ARRAY_SIZE(adl_community5_groups), + } +}; + +const struct pad_community *soc_gpio_get_community(size_t *num_communities) +{ + *num_communities = ARRAY_SIZE(adl_communities); + return adl_communities; +} + +const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num) +{ + static const struct pmc_to_gpio_route routes[] = { + { PMC_GPP_I, GPP_I }, + { PMC_GPP_R, GPP_R }, + { PMC_GPP_J, GPP_J }, + { PMC_GPD, GPD }, + { PMC_GPP_D, GPP_D }, + { PMC_GPP_S, GPP_S }, + { PMC_GPP_E, GPP_E }, + { PMC_GPP_K, GPP_K }, + { PMC_GPP_F, GPP_F }, + { PMC_GPP_A, GPP_A }, + { PMC_GPP_C, GPP_C }, + { PMC_GPP_B, GPP_B }, + { PMC_GPP_G, GPP_G }, + { PMC_GPP_H, GPP_H }, + }; + *num = ARRAY_SIZE(routes); + return routes; +}; diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h index 407c3b7..0c9bc4e 100644 --- a/src/soc/intel/alderlake/include/soc/gpio.h +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -3,17 +3,24 @@ #ifndef _SOC_ALDERLAKE_GPIO_H_ #define _SOC_ALDERLAKE_GPIO_H_ -#include <soc/gpio_defs.h> #include <intelblocks/gpio.h> -#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#include <soc/gpio_defs_pch_s.h> +#define CROS_GPIO_NAME "INTC1056" +#define CROS_GPIO_DEVICE_NAME "INTC1056:00" +#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#include <soc/gpio_defs.h> #define CROS_GPIO_NAME "INTC1057" #define CROS_GPIO_DEVICE_NAME "INTC1057:00" #else +#include <soc/gpio_defs.h> #define CROS_GPIO_NAME "INTC1055" #define CROS_GPIO_DEVICE_NAME "INTC1055:00" #endif +#include <intelblocks/gpio.h> + /* Enable GPIO community power management configuration */ #define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \ diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h b/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h new file mode 100644 index 0000000..6e9613c --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_ALDERLAKE_GPIO_DEFS_PCH_H_H_ +#define _SOC_ALDERLAKE_GPIO_DEFS_PCH_H_H_ + +#ifndef __ACPI__ +#include <stddef.h> +#endif +#include <soc/gpio_soc_defs_pch_s.h> + +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ + +#define NUM_GPIO_COMx_GPI_REGS(n) \ + (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP) + +#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS) +#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) +#define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) +#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS)) + +#define PAD_CFG_LOCK_OFFSET 0x110 + +/* + * IOxAPIC IRQs for the GPIOs + */ + +/* Group I */ +#define GPP_I0_IRQ 0x18 +#define GPP_I1_IRQ 0x19 +#define GPP_I2_IRQ 0x1A +#define GPP_I3_IRQ 0x1B +#define GPP_I4_IRQ 0x1C +#define GPP_I5_IRQ 0x1D +#define GPP_I6_IRQ 0x1E +#define GPP_I7_IRQ 0x20 +#define GPP_I8_IRQ 0x21 +#define GPP_I9_IRQ 0x22 +#define GPP_I10_IRQ 0x23 +#define GPP_I11_IRQ 0x24 +#define GPP_I12_IRQ 0x25 +#define GPP_I13_IRQ 0x26 +#define GPP_I14_IRQ 0x27 +#define GPP_I15_IRQ 0x28 +#define GPP_I16_IRQ 0x29 +#define GPP_I17_IRQ 0x2A +#define GPP_I18_IRQ 0x2B +#define GPP_I19_IRQ 0x2C +#define GPP_I20_IRQ 0x2D +#define GPP_I21_IRQ 0x2E +#define GPP_I22_IRQ 0x30 + +/* Group R */ +#define GPP_R0_IRQ 0x31 +#define GPP_R1_IRQ 0x32 +#define GPP_R2_IRQ 0x33 +#define GPP_R3_IRQ 0x34 +#define GPP_R4_IRQ 0x35 +#define GPP_R5_IRQ 0x36 +#define GPP_R6_IRQ 0x37 +#define GPP_R7_IRQ 0x38 +#define GPP_R8_IRQ 0x39 +#define GPP_R9_IRQ 0x3A +#define GPP_R10_IRQ 0x3B +#define GPP_R11_IRQ 0x3C +#define GPP_R12_IRQ 0x3D +#define GPP_R13_IRQ 0x3E +#define GPP_R14_IRQ 0x3F +#define GPP_R15_IRQ 0x40 +#define GPP_R16_IRQ 0x41 +#define GPP_R17_IRQ 0x42 +#define GPP_R18_IRQ 0x43 +#define GPP_R19_IRQ 0x44 +#define GPP_R20_IRQ 0x45 +#define GPP_R21_IRQ 0x46 + +/* Group J */ +#define GPP_J0_IRQ 0x47 +#define GPP_J1_IRQ 0x48 +#define GPP_J2_IRQ 0x49 +#define GPP_J3_IRQ 0x4A +#define GPP_J4_IRQ 0x4B +#define GPP_J5_IRQ 0x4C +#define GPP_J6_IRQ 0x4D +#define GPP_J7_IRQ 0x4E +#define GPP_J8_IRQ 0x50 +#define GPP_J9_IRQ 0x51 +#define GPP_J10_IRQ 0x52 +#define GPP_J11_IRQ 0x53 + +/* Group B */ +#define GPP_B0_IRQ 0x50 +#define GPP_B1_IRQ 0x51 +#define GPP_B2_IRQ 0x52 +#define GPP_B3_IRQ 0x53 +#define GPP_B4_IRQ 0x54 +#define GPP_B5_IRQ 0x55 +#define GPP_B6_IRQ 0x56 +#define GPP_B7_IRQ 0x57 +#define GPP_B8_IRQ 0x58 +#define GPP_B9_IRQ 0x59 +#define GPP_B10_IRQ 0x5A +#define GPP_B11_IRQ 0x5B +#define GPP_B12_IRQ 0x5C +#define GPP_B13_IRQ 0x5D +#define GPP_B14_IRQ 0x5E +#define GPP_B15_IRQ 0x5F +#define GPP_B16_IRQ 0x60 +#define GPP_B17_IRQ 0x61 +#define GPP_B18_IRQ 0x62 +#define GPP_B19_IRQ 0x63 +#define GPP_B20_IRQ 0x64 +#define GPP_B21_IRQ 0x65 +#define GPP_B22_IRQ 0x66 +#define GPP_B23_IRQ 0x67 + +/* Group G */ +#define GPP_G0_IRQ 0x68 +#define GPP_G1_IRQ 0x69 +#define GPP_G2_IRQ 0x6A +#define GPP_G3_IRQ 0x6B +#define GPP_G4_IRQ 0x6C +#define GPP_G5_IRQ 0x6D +#define GPP_G6_IRQ 0x6E +#define GPP_G7_IRQ 0x6F + +/* Group H */ +#define GPP_H0_IRQ 0x70 +#define GPP_H1_IRQ 0x71 +#define GPP_H2_IRQ 0x72 +#define GPP_H3_IRQ 0x73 +#define GPP_H4_IRQ 0x74 +#define GPP_H5_IRQ 0x75 +#define GPP_H6_IRQ 0x76 +#define GPP_H7_IRQ 0x77 +#define GPP_H8_IRQ 0x18 +#define GPP_H9_IRQ 0x19 +#define GPP_H10_IRQ 0x20 +#define GPP_H11_IRQ 0x21 +#define GPP_H12_IRQ 0x22 +#define GPP_H13_IRQ 0x23 +#define GPP_H14_IRQ 0x24 +#define GPP_H15_IRQ 0x25 +#define GPP_H16_IRQ 0x26 +#define GPP_H17_IRQ 0x27 +#define GPP_H18_IRQ 0x28 +#define GPP_H19_IRQ 0x29 +#define GPP_H20_IRQ 0x2A +#define GPP_H21_IRQ 0x2B +#define GPP_H22_IRQ 0x2C +#define GPP_H23_IRQ 0x2D + +/* Group GPD */ +#define GPD0_IRQ 0x60 +#define GPD1_IRQ 0x61 +#define GPD2_IRQ 0x62 +#define GPD3_IRQ 0x63 +#define GPD4_IRQ 0x64 +#define GPD5_IRQ 0x65 +#define GPD6_IRQ 0x66 +#define GPD7_IRQ 0x67 +#define GPD8_IRQ 0x68 +#define GPD9_IRQ 0x69 +#define GPD10_IRQ 0x6A +#define GPD11_IRQ 0x6B +#define GPD12_IRQ 0x6C + +/* Group A */ +#define GPP_A0_IRQ 0x18 +#define GPP_A1_IRQ 0x19 +#define GPP_A2_IRQ 0x20 +#define GPP_A3_IRQ 0x21 +#define GPP_A4_IRQ 0x22 +#define GPP_A5_IRQ 0x23 +#define GPP_A6_IRQ 0x24 +#define GPP_A7_IRQ 0x25 +#define GPP_A8_IRQ 0x26 +#define GPP_A9_IRQ 0x27 +#define GPP_A10_IRQ 0x28 +#define GPP_A11_IRQ 0x29 +#define GPP_A12_IRQ 0x2A +#define GPP_A13_IRQ 0x2B +#define GPP_A14_IRQ 0x2C + +/* Group C */ +#define GPP_C0_IRQ 0x2D +#define GPP_C1_IRQ 0x2E +#define GPP_C2_IRQ 0x2F +#define GPP_C3_IRQ 0x30 +#define GPP_C4_IRQ 0x31 +#define GPP_C5_IRQ 0x32 +#define GPP_C6_IRQ 0x33 +#define GPP_C7_IRQ 0x34 +#define GPP_C8_IRQ 0x35 +#define GPP_C9_IRQ 0x36 +#define GPP_C10_IRQ 0x37 +#define GPP_C11_IRQ 0x38 +#define GPP_C12_IRQ 0x39 +#define GPP_C13_IRQ 0x3A +#define GPP_C14_IRQ 0x3B +#define GPP_C15_IRQ 0x3C +#define GPP_C16_IRQ 0x3D +#define GPP_C17_IRQ 0x3E +#define GPP_C18_IRQ 0x3F +#define GPP_C19_IRQ 0x40 +#define GPP_C20_IRQ 0x41 +#define GPP_C21_IRQ 0x42 +#define GPP_C22_IRQ 0x43 +#define GPP_C23_IRQ 0x44 + +/* Group S */ +#define GPP_S0_IRQ 0x30 +#define GPP_S1_IRQ 0x31 +#define GPP_S2_IRQ 0x32 +#define GPP_S3_IRQ 0x33 +#define GPP_S4_IRQ 0x34 +#define GPP_S5_IRQ 0x35 +#define GPP_S6_IRQ 0x36 +#define GPP_S7_IRQ 0x37 + +/* Group E */ +#define GPP_E0_IRQ 0x38 +#define GPP_E1_IRQ 0x39 +#define GPP_E2_IRQ 0x3A +#define GPP_E3_IRQ 0x3B +#define GPP_E4_IRQ 0x3C +#define GPP_E5_IRQ 0x3D +#define GPP_E6_IRQ 0x3E +#define GPP_E7_IRQ 0x3F +#define GPP_E8_IRQ 0x40 +#define GPP_E9_IRQ 0x41 +#define GPP_E10_IRQ 0x42 +#define GPP_E11_IRQ 0x43 +#define GPP_E12_IRQ 0x44 +#define GPP_E13_IRQ 0x45 +#define GPP_E14_IRQ 0x46 +#define GPP_E15_IRQ 0x47 +#define GPP_E16_IRQ 0x48 +#define GPP_E17_IRQ 0x49 +#define GPP_E18_IRQ 0x4A +#define GPP_E19_IRQ 0x4B +#define GPP_E20_IRQ 0x4C +#define GPP_E21_IRQ 0x4D + +/* Group K */ +#define GPP_K0_IRQ 0x4E +#define GPP_K1_IRQ 0x50 +#define GPP_K2_IRQ 0x51 +#define GPP_K3_IRQ 0x52 +#define GPP_K4_IRQ 0x53 +#define GPP_K5_IRQ 0x54 +#define GPP_K6_IRQ 0x55 +#define GPP_K7_IRQ 0x56 +#define GPP_K8_IRQ 0x57 +#define GPP_K9_IRQ 0x58 +#define GPP_K10_IRQ 0x59 +#define GPP_K11_IRQ 0x5A + +/* Group F */ +#define GPP_F0_IRQ 0x5B +#define GPP_F1_IRQ 0x5C +#define GPP_F2_IRQ 0x5D +#define GPP_F3_IRQ 0x5E +#define GPP_F4_IRQ 0x60 +#define GPP_F5_IRQ 0x61 +#define GPP_F6_IRQ 0x62 +#define GPP_F7_IRQ 0x63 +#define GPP_F8_IRQ 0x64 +#define GPP_F9_IRQ 0x65 +#define GPP_F10_IRQ 0x66 +#define GPP_F11_IRQ 0x67 +#define GPP_F12_IRQ 0x68 +#define GPP_F13_IRQ 0x69 +#define GPP_F14_IRQ 0x6A +#define GPP_F15_IRQ 0x6B +#define GPP_F16_IRQ 0x6C +#define GPP_F17_IRQ 0x6D +#define GPP_F18_IRQ 0x6E +#define GPP_F19_IRQ 0x6F +#define GPP_F20_IRQ 0x70 +#define GPP_F21_IRQ 0x71 +#define GPP_F22_IRQ 0x72 +#define GPP_F23_IRQ 0x73 + +/* Group D */ +#define GPP_D0_IRQ 0x70 +#define GPP_D1_IRQ 0x71 +#define GPP_D2_IRQ 0x72 +#define GPP_D3_IRQ 0x73 +#define GPP_D4_IRQ 0x74 +#define GPP_D5_IRQ 0x75 +#define GPP_D6_IRQ 0x76 +#define GPP_D7_IRQ 0x77 +#define GPP_D8_IRQ 0x18 +#define GPP_D9_IRQ 0x19 +#define GPP_D10_IRQ 0x20 +#define GPP_D11_IRQ 0x21 +#define GPP_D12_IRQ 0x22 +#define GPP_D13_IRQ 0x23 +#define GPP_D14_IRQ 0x24 +#define GPP_D15_IRQ 0x25 +#define GPP_D16_IRQ 0x26 +#define GPP_D17_IRQ 0x27 +#define GPP_D18_IRQ 0x28 +#define GPP_D19_IRQ 0x29 +#define GPP_D20_IRQ 0x2A +#define GPP_D21_IRQ 0x2B +#define GPP_D22_IRQ 0x2C +#define GPP_D23_IRQ 0x2D + +/* Register defines. */ +#define GPIO_MISCCFG 0x10 +#define GPE_DW_SHIFT 8 +#define GPE_DW_MASK 0xfff00 +#define HOSTSW_OWN_REG_0 0x200 +#define GPI_INT_STS_0 0x220 +#define GPI_INT_EN_0 0x110 +#define GPI_SMI_STS_0 0x280 +#define GPI_SMI_EN_0 0x2A0 +#define PAD_CFG_BASE 0x700 + +#endif diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h new file mode 100644 index 0000000..2c9134e --- /dev/null +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h @@ -0,0 +1,524 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _SOC_ALDERLAKE_GPIO_SOC_DEFS_PCH_H_H_ +#define _SOC_ALDERLAKE_GPIO_SOC_DEFS_PCH_H_H_ + +#define INC(x) ((x) + 1) +/* + * Most of the fixed numbers and macros are based on the GPP groups. + * The GPIO groups are accessed through register blocks called + * communities. + * + * Refer to Alder Lake PCH-S EDS Chapter 26, MISCCFG register offset 0x10 + * for each GPIO community to get GPIO group to GPE_DWx assignment. + */ +#define GPP_I 0x0 +#define GPP_R INC(GPP_I) +#define GPP_J INC(GPP_R) +#define GPD 0x4 +#define GPP_D INC(GPD) +#define GPP_S INC(GPP_D) +#define GPP_E INC(GPP_S) +#define GPP_K INC(GPP_E) +#define GPP_F INC(GPP_K) +#define GPP_A INC(GPP_F) +#define GPP_C INC(GPP_A) +#define GPP_B INC(GPP_C) +#define GPP_G INC(GPP_B) +#define GPP_H INC(GPP_G) + +#define GPIO_MAX_NUM_PER_GROUP 26 + +#define COMM_0 0 +#define COMM_1 INC(COMM_0) +#define COMM_2 INC(COMM_1) +#define COMM_3 INC(COMM_2) +#define COMM_4 INC(COMM_3) +#define COMM_5 INC(COMM_4) + +/* Group I */ +#define GPP_I0 0 +#define GPP_I1 INC(GPP_I0) +#define GPP_I2 INC(GPP_I1) +#define GPP_I3 INC(GPP_I2) +#define GPP_I4 INC(GPP_I3) +#define GPP_I5 INC(GPP_I4) +#define GPP_I6 INC(GPP_I5) +#define GPP_I7 INC(GPP_I6) +#define GPP_I8 INC(GPP_I7) +#define GPP_I9 INC(GPP_I8) +#define GPP_I10 INC(GPP_I9) +#define GPP_I11 INC(GPP_I10) +#define GPP_I12 INC(GPP_I11) +#define GPP_I13 INC(GPP_I12) +#define GPP_I14 INC(GPP_I13) +#define GPP_I15 INC(GPP_I14) +#define GPP_I16 INC(GPP_I15) +#define GPP_I17 INC(GPP_I16) +#define GPP_I18 INC(GPP_I17) +#define GPP_I19 INC(GPP_I18) +#define GPP_I20 INC(GPP_I19) +#define GPP_I21 INC(GPP_I20) +#define GPP_I22 INC(GPP_I21) +#define GPP_GSPI0_CLK_LOOPBK INC(GPP_I17) +#define GPP_GSPI1_CLK_LOOPBK INC(GPP_I18) + +/* Group R */ +#define GPP_R0 INC(GPP_GSPI1_CLK_LOOPBK) +#define GPP_R1 INC(GPP_R0) +#define GPP_R2 INC(GPP_R1) +#define GPP_R3 INC(GPP_R2) +#define GPP_R4 INC(GPP_R3) +#define GPP_R5 INC(GPP_R4) +#define GPP_R6 INC(GPP_R5) +#define GPP_R7 INC(GPP_R6) +#define GPP_R8 INC(GPP_R7) +#define GPP_R9 INC(GPP_R8) +#define GPP_R10 INC(GPP_R9) +#define GPP_R11 INC(GPP_R10) +#define GPP_R12 INC(GPP_R11) +#define GPP_R13 INC(GPP_R12) +#define GPP_R14 INC(GPP_R13) +#define GPP_R15 INC(GPP_R14) +#define GPP_R16 INC(GPP_R15) +#define GPP_R17 INC(GPP_R16) +#define GPP_R18 INC(GPP_R17) +#define GPP_R19 INC(GPP_R18) +#define GPP_R20 INC(GPP_R19) +#define GPP_R21 INC(GPP_R20) +#define GPP_GSPI2_CLK_LOOPBK INC(GPP_R21) + +/* Group J */ +#define GPP_J0 INC(GPP_GSPI2_CLK_LOOPBK) +#define GPP_J1 INC(GPP_J0) +#define GPP_J2 INC(GPP_J1) +#define GPP_J3 INC(GPP_J2) +#define GPP_J4 INC(GPP_J3) +#define GPP_J5 INC(GPP_J4) +#define GPP_J6 INC(GPP_J5) +#define GPP_J7 INC(GPP_J6) +#define GPP_J8 INC(GPP_J7) +#define GPP_J9 INC(GPP_J8) +#define GPP_J10 INC(GPP_J9) +#define GPP_J11 INC(GPP_J10) + +/* Group vGPIO */ +#define GPP_VGPIO_0 INC(GPP_J11) +#define GPP_VGPIO_4 INC(GPP_VGPIO_0) +#define GPP_VGPIO_5 INC(GPP_VGPIO_4) +#define GPP_VGPIO_6 INC(GPP_VGPIO_5) +#define GPP_VGPIO_7 INC(GPP_VGPIO_6) +#define GPP_VGPIO_8 INC(GPP_VGPIO_7) +#define GPP_VGPIO_9 INC(GPP_VGPIO_8) +#define GPP_VGPIO_10 INC(GPP_VGPIO_9) +#define GPP_VGPIO_11 INC(GPP_VGPIO_10) +#define GPP_VGPIO_12 INC(GPP_VGPIO_11) +#define GPP_VGPIO_13 INC(GPP_VGPIO_12) +#define GPP_VGPIO_18 INC(GPP_VGPIO_13) +#define GPP_VGPIO_19 INC(GPP_VGPIO_18) +#define GPP_VGPIO_20 INC(GPP_VGPIO_19) +#define GPP_VGPIO_21 INC(GPP_VGPIO_20) +#define GPP_VGPIO_22 INC(GPP_VGPIO_21) +#define GPP_VGPIO_23 INC(GPP_VGPIO_22) +#define GPP_VGPIO_24 INC(GPP_VGPIO_23) +#define GPP_VGPIO_25 INC(GPP_VGPIO_24) +#define GPP_VGPIO_30 INC(GPP_VGPIO_25) +#define GPP_VGPIO_31 INC(GPP_VGPIO_30) +#define GPP_VGPIO_32 INC(GPP_VGPIO_31) +#define GPP_VGPIO_33 INC(GPP_VGPIO_32) +#define GPP_VGPIO_34 INC(GPP_VGPIO_33) +#define GPP_VGPIO_35 INC(GPP_VGPIO_34) +#define GPP_VGPIO_36 INC(GPP_VGPIO_35) +#define GPP_VGPIO_37 INC(GPP_VGPIO_36) + +/* Group vGPIO_0 */ +#define GPP_VGPIO_USB_0 INC(GPP_VGPIO_37) +#define GPP_VGPIO_USB_1 INC(GPP_VGPIO_USB_0) +#define GPP_VGPIO_USB_2 INC(GPP_VGPIO_USB_1) +#define GPP_VGPIO_USB_3 INC(GPP_VGPIO_USB_2) +#define GPP_VGPIO_USB_8 INC(GPP_VGPIO_USB_3) +#define GPP_VGPIO_USB_9 INC(GPP_VGPIO_USB_8) +#define GPP_VGPIO_USB_10 INC(GPP_VGPIO_USB_9) +#define GPP_VGPIO_USB_11 INC(GPP_VGPIO_USB_10) + +#define GPIO_COM0_START GPP_I0 +#define GPIO_COM0_END GPP_VGPIO_USB_11 +#define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) + +/* Group B */ +#define GPP_B0 INC(GPP_VGPIO_USB_11) +#define GPP_B1 INC(GPP_B0) +#define GPP_B2 INC(GPP_B1) +#define GPP_B3 INC(GPP_B2) +#define GPP_B4 INC(GPP_B3) +#define GPP_B5 INC(GPP_B4) +#define GPP_B6 INC(GPP_B5) +#define GPP_B7 INC(GPP_B6) +#define GPP_B8 INC(GPP_B7) +#define GPP_B9 INC(GPP_B8) +#define GPP_B10 INC(GPP_B9) +#define GPP_B11 INC(GPP_B10) +#define GPP_B12 INC(GPP_B11) +#define GPP_B13 INC(GPP_B12) +#define GPP_B14 INC(GPP_B13) +#define GPP_B15 INC(GPP_B14) +#define GPP_B16 INC(GPP_B15) +#define GPP_B17 INC(GPP_B16) +#define GPP_B18 INC(GPP_B17) +#define GPP_B19 INC(GPP_B18) +#define GPP_B20 INC(GPP_B19) +#define GPP_B21 INC(GPP_B20) +#define GPP_B22 INC(GPP_B21) +#define GPP_B23 INC(GPP_B22) + +/* Group G */ +#define GPP_G0 INC(GPP_B23) +#define GPP_G1 INC(GPP_G0) +#define GPP_G2 INC(GPP_G1) +#define GPP_G3 INC(GPP_G2) +#define GPP_G4 INC(GPP_G3) +#define GPP_G5 INC(GPP_G4) +#define GPP_G6 INC(GPP_G5) +#define GPP_G7 INC(GPP_G6) + +/* Group H */ +#define GPP_H0 INC(GPP_G7) +#define GPP_H1 INC(GPP_H0) +#define GPP_H2 INC(GPP_H1) +#define GPP_H3 INC(GPP_H2) +#define GPP_H4 INC(GPP_H3) +#define GPP_H5 INC(GPP_H4) +#define GPP_H6 INC(GPP_H5) +#define GPP_H7 INC(GPP_H6) +#define GPP_H8 INC(GPP_H7) +#define GPP_H9 INC(GPP_H8) +#define GPP_H10 INC(GPP_H9) +#define GPP_H11 INC(GPP_H10) +#define GPP_H12 INC(GPP_H11) +#define GPP_H13 INC(GPP_H12) +#define GPP_H14 INC(GPP_H13) +#define GPP_H15 INC(GPP_H14) +#define GPP_H16 INC(GPP_H15) +#define GPP_H17 INC(GPP_H16) +#define GPP_H18 INC(GPP_H17) +#define GPP_H19 INC(GPP_H18) +#define GPP_H20 INC(GPP_H19) +#define GPP_H21 INC(GPP_H20) +#define GPP_H22 INC(GPP_H21) +#define GPP_H23 INC(GPP_H22) + +#define GPIO_COM1_START GPP_B0 +#define GPIO_COM1_END GPP_H23 +#define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) + +/* Group GPD */ +#define GPD0 INC(GPP_H23) +#define GPD1 INC(GPD0) +#define GPD2 INC(GPD1) +#define GPD3 INC(GPD2) +#define GPD4 INC(GPD3) +#define GPD5 INC(GPD4) +#define GPD6 INC(GPD5) +#define GPD7 INC(GPD6) +#define GPD8 INC(GPD7) +#define GPD9 INC(GPD8) +#define GPD10 INC(GPD9) +#define GPD11 INC(GPD10) +#define GPD12 INC(GPD11) +#define GPD_SLP_LANB INC(GPD12) +#define GPD_SLP_SUSB INC(GPD_SLP_LANB) +#define GPD_WAKEB INC(GPD_SLP_SUSB) +#define GPD_DRAM_RESETB INC(GPD_WAKEB) + +#define GPIO_COM2_START GPD0 +#define GPIO_COM2_END GPD_DRAM_RESETB +#define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) + +/* Group SPI */ +#define GPP_SPI0_IO_2 INC(GPD_DRAM_RESETB) +#define GPP_SPI0_IO_3 INC(GPP_SPI0_IO_2) +#define GPP_SPI0_MOSI_IO_0 INC(GPP_SPI0_IO_3) +#define GPP_SPI0_MISO_IO_1 INC(GPP_SPI0_MOSI_IO_0) +#define GPP_SPI0_TPM_CSB INC(GPP_SPI0_MISO_IO_1) +#define GPP_SPI0_FLASH_0_CSB INC(GPP_SPI0_TPM_CSB) +#define GPP_SPI0_FLASH_1_CSB INC(GPP_SPI0_FLASH_0_CSB) +#define GPP_SPI0_CLK INC(GPP_SPI0_FLASH_1_CSB) +#define GPP_SPI0_CLK_LOOPBK INC(GPP_SPI0_CLK) + +/* Group A */ +#define GPP_A0 INC(GPP_SPI0_CLK_LOOPBK) +#define GPP_A1 INC(GPP_A0) +#define GPP_A2 INC(GPP_A1) +#define GPP_A3 INC(GPP_A2) +#define GPP_A4 INC(GPP_A3) +#define GPP_A5 INC(GPP_A4) +#define GPP_A6 INC(GPP_A5) +#define GPP_A7 INC(GPP_A6) +#define GPP_A8 INC(GPP_A7) +#define GPP_A9 INC(GPP_A8) +#define GPP_A10 INC(GPP_A9) +#define GPP_A11 INC(GPP_A10) +#define GPP_A12 INC(GPP_A11) +#define GPP_A13 INC(GPP_A12) +#define GPP_A14 INC(GPP_A13) +#define GPP_ESPI_CLK_LOOPBK INC(GPP_A14) + +/* Group C */ +#define GPP_C0 INC(GPP_SPI0_CLK_LOOPBK) +#define GPP_C1 INC(GPP_C0) +#define GPP_C2 INC(GPP_C1) +#define GPP_C3 INC(GPP_C2) +#define GPP_C4 INC(GPP_C3) +#define GPP_C5 INC(GPP_C4) +#define GPP_C6 INC(GPP_C5) +#define GPP_C7 INC(GPP_C6) +#define GPP_C8 INC(GPP_C7) +#define GPP_C9 INC(GPP_C8) +#define GPP_C10 INC(GPP_C9) +#define GPP_C11 INC(GPP_C10) +#define GPP_C12 INC(GPP_C11) +#define GPP_C13 INC(GPP_C12) +#define GPP_C14 INC(GPP_C13) +#define GPP_C15 INC(GPP_C14) +#define GPP_C16 INC(GPP_C15) +#define GPP_C17 INC(GPP_C16) +#define GPP_C18 INC(GPP_C17) +#define GPP_C19 INC(GPP_C18) +#define GPP_C20 INC(GPP_C19) +#define GPP_C21 INC(GPP_C20) +#define GPP_C22 INC(GPP_C21) +#define GPP_C23 INC(GPP_C22) + +/* Group vGPIO_3 */ +#define GPP_VGPIO_PCIE_0 INC(GPP_C23) +#define GPP_VGPIO_PCIE_1 INC(GPP_VGPIO_PCIE_0) +#define GPP_VGPIO_PCIE_2 INC(GPP_VGPIO_PCIE_1) +#define GPP_VGPIO_PCIE_3 INC(GPP_VGPIO_PCIE_2) +#define GPP_VGPIO_PCIE_4 INC(GPP_VGPIO_PCIE_3) +#define GPP_VGPIO_PCIE_5 INC(GPP_VGPIO_PCIE_4) +#define GPP_VGPIO_PCIE_6 INC(GPP_VGPIO_PCIE_5) +#define GPP_VGPIO_PCIE_7 INC(GPP_VGPIO_PCIE_6) +#define GPP_VGPIO_PCIE_8 INC(GPP_VGPIO_PCIE_7) +#define GPP_VGPIO_PCIE_9 INC(GPP_VGPIO_PCIE_8) +#define GPP_VGPIO_PCIE_10 INC(GPP_VGPIO_PCIE_9) +#define GPP_VGPIO_PCIE_11 INC(GPP_VGPIO_PCIE_10) +#define GPP_VGPIO_PCIE_12 INC(GPP_VGPIO_PCIE_11) +#define GPP_VGPIO_PCIE_13 INC(GPP_VGPIO_PCIE_12) +#define GPP_VGPIO_PCIE_14 INC(GPP_VGPIO_PCIE_13) +#define GPP_VGPIO_PCIE_15 INC(GPP_VGPIO_PCIE_14) +#define GPP_VGPIO_PCIE_16 INC(GPP_VGPIO_PCIE_15) +#define GPP_VGPIO_PCIE_17 INC(GPP_VGPIO_PCIE_16) +#define GPP_VGPIO_PCIE_18 INC(GPP_VGPIO_PCIE_17) +#define GPP_VGPIO_PCIE_19 INC(GPP_VGPIO_PCIE_18) +#define GPP_VGPIO_PCIE_20 INC(GPP_VGPIO_PCIE_19) +#define GPP_VGPIO_PCIE_21 INC(GPP_VGPIO_PCIE_20) +#define GPP_VGPIO_PCIE_22 INC(GPP_VGPIO_PCIE_21) +#define GPP_VGPIO_PCIE_23 INC(GPP_VGPIO_PCIE_22) +#define GPP_VGPIO_PCIE_24 INC(GPP_VGPIO_PCIE_23) +#define GPP_VGPIO_PCIE_25 INC(GPP_VGPIO_PCIE_24) +#define GPP_VGPIO_PCIE_26 INC(GPP_VGPIO_PCIE_25) +#define GPP_VGPIO_PCIE_27 INC(GPP_VGPIO_PCIE_26) +#define GPP_VGPIO_PCIE_28 INC(GPP_VGPIO_PCIE_27) +#define GPP_VGPIO_PCIE_29 INC(GPP_VGPIO_PCIE_28) +#define GPP_VGPIO_PCIE_30 INC(GPP_VGPIO_PCIE_29) +#define GPP_VGPIO_PCIE_31 INC(GPP_VGPIO_PCIE_30) +#define GPP_VGPIO_PCIE_32 INC(GPP_VGPIO_PCIE_31) +#define GPP_VGPIO_PCIE_33 INC(GPP_VGPIO_PCIE_32) +#define GPP_VGPIO_PCIE_34 INC(GPP_VGPIO_PCIE_33) +#define GPP_VGPIO_PCIE_35 INC(GPP_VGPIO_PCIE_34) +#define GPP_VGPIO_PCIE_36 INC(GPP_VGPIO_PCIE_35) +#define GPP_VGPIO_PCIE_37 INC(GPP_VGPIO_PCIE_36) +#define GPP_VGPIO_PCIE_38 INC(GPP_VGPIO_PCIE_37) +#define GPP_VGPIO_PCIE_39 INC(GPP_VGPIO_PCIE_38) +#define GPP_VGPIO_PCIE_40 INC(GPP_VGPIO_PCIE_39) +#define GPP_VGPIO_PCIE_41 INC(GPP_VGPIO_PCIE_40) +#define GPP_VGPIO_PCIE_42 INC(GPP_VGPIO_PCIE_41) +#define GPP_VGPIO_PCIE_43 INC(GPP_VGPIO_PCIE_42) +#define GPP_VGPIO_PCIE_44 INC(GPP_VGPIO_PCIE_43) +#define GPP_VGPIO_PCIE_45 INC(GPP_VGPIO_PCIE_44) +#define GPP_VGPIO_PCIE_46 INC(GPP_VGPIO_PCIE_45) +#define GPP_VGPIO_PCIE_47 INC(GPP_VGPIO_PCIE_46) +#define GPP_VGPIO_PCIE_48 INC(GPP_VGPIO_PCIE_47) +#define GPP_VGPIO_PCIE_49 INC(GPP_VGPIO_PCIE_48) +#define GPP_VGPIO_PCIE_50 INC(GPP_VGPIO_PCIE_49) +#define GPP_VGPIO_PCIE_51 INC(GPP_VGPIO_PCIE_50) +#define GPP_VGPIO_PCIE_52 INC(GPP_VGPIO_PCIE_51) +#define GPP_VGPIO_PCIE_53 INC(GPP_VGPIO_PCIE_52) +#define GPP_VGPIO_PCIE_54 INC(GPP_VGPIO_PCIE_53) +#define GPP_VGPIO_PCIE_55 INC(GPP_VGPIO_PCIE_54) +#define GPP_VGPIO_PCIE_56 INC(GPP_VGPIO_PCIE_55) +#define GPP_VGPIO_PCIE_57 INC(GPP_VGPIO_PCIE_56) +#define GPP_VGPIO_PCIE_58 INC(GPP_VGPIO_PCIE_57) +#define GPP_VGPIO_PCIE_59 INC(GPP_VGPIO_PCIE_58) +#define GPP_VGPIO_PCIE_60 INC(GPP_VGPIO_PCIE_59) +#define GPP_VGPIO_PCIE_61 INC(GPP_VGPIO_PCIE_60) +#define GPP_VGPIO_PCIE_62 INC(GPP_VGPIO_PCIE_61) +#define GPP_VGPIO_PCIE_63 INC(GPP_VGPIO_PCIE_62) +#define GPP_VGPIO_PCIE_64 INC(GPP_VGPIO_PCIE_63) +#define GPP_VGPIO_PCIE_65 INC(GPP_VGPIO_PCIE_64) +#define GPP_VGPIO_PCIE_66 INC(GPP_VGPIO_PCIE_65) +#define GPP_VGPIO_PCIE_67 INC(GPP_VGPIO_PCIE_66) +#define GPP_VGPIO_PCIE_68 INC(GPP_VGPIO_PCIE_67) +#define GPP_VGPIO_PCIE_69 INC(GPP_VGPIO_PCIE_68) +#define GPP_VGPIO_PCIE_70 INC(GPP_VGPIO_PCIE_69) +#define GPP_VGPIO_PCIE_71 INC(GPP_VGPIO_PCIE_70) +#define GPP_VGPIO_PCIE_72 INC(GPP_VGPIO_PCIE_71) +#define GPP_VGPIO_PCIE_73 INC(GPP_VGPIO_PCIE_72) +#define GPP_VGPIO_PCIE_74 INC(GPP_VGPIO_PCIE_73) +#define GPP_VGPIO_PCIE_75 INC(GPP_VGPIO_PCIE_74) +#define GPP_VGPIO_PCIE_76 INC(GPP_VGPIO_PCIE_75) +#define GPP_VGPIO_PCIE_77 INC(GPP_VGPIO_PCIE_76) +#define GPP_VGPIO_PCIE_78 INC(GPP_VGPIO_PCIE_77) +#define GPP_VGPIO_PCIE_79 INC(GPP_VGPIO_PCIE_78) +#define GPP_VGPIO_PCIE_80 INC(GPP_VGPIO_PCIE_79) +#define GPP_VGPIO_PCIE_81 INC(GPP_VGPIO_PCIE_80) +#define GPP_VGPIO_PCIE_82 INC(GPP_VGPIO_PCIE_81) +#define GPP_VGPIO_PCIE_83 INC(GPP_VGPIO_PCIE_82) + +#define GPIO_COM3_START GPP_SPI0_IO_2 +#define GPIO_COM3_END GPP_VGPIO_PCIE_83 +#define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1) + +/* Group S */ +#define GPP_S0 INC(GPP_VGPIO_PCIE_83) +#define GPP_S1 INC(GPP_S0) +#define GPP_S2 INC(GPP_S1) +#define GPP_S3 INC(GPP_S2) +#define GPP_S4 INC(GPP_S3) +#define GPP_S5 INC(GPP_S4) +#define GPP_S6 INC(GPP_S5) +#define GPP_S7 INC(GPP_S6) + +/* Group E */ +#define GPP_E0 INC(GPP_S7) +#define GPP_E1 INC(GPP_E0) +#define GPP_E2 INC(GPP_E1) +#define GPP_E3 INC(GPP_E2) +#define GPP_E4 INC(GPP_E3) +#define GPP_E5 INC(GPP_E4) +#define GPP_E6 INC(GPP_E5) +#define GPP_E7 INC(GPP_E6) +#define GPP_E8 INC(GPP_E7) +#define GPP_E9 INC(GPP_E8) +#define GPP_E10 INC(GPP_E9) +#define GPP_E11 INC(GPP_E10) +#define GPP_E12 INC(GPP_E11) +#define GPP_E13 INC(GPP_E12) +#define GPP_E14 INC(GPP_E13) +#define GPP_E15 INC(GPP_E14) +#define GPP_E16 INC(GPP_E15) +#define GPP_E17 INC(GPP_E16) +#define GPP_E18 INC(GPP_E17) +#define GPP_E19 INC(GPP_E18) +#define GPP_E20 INC(GPP_E19) +#define GPP_E21 INC(GPP_E20) +#define GPP_SPI1_THC0_CLK_LOOPBK INC(GPP_E21) + +/* Group K */ +#define GPP_K0 INC(GPP_SPI1_THC0_CLK_LOOPBK) +#define GPP_K1 INC(GPP_K0) +#define GPP_K2 INC(GPP_K1) +#define GPP_K3 INC(GPP_K2) +#define GPP_K4 INC(GPP_K3) +#define GPP_K5 INC(GPP_K4) +#define GPP_K6 INC(GPP_K5) +#define GPP_K7 INC(GPP_K6) +#define GPP_K8 INC(GPP_K7) +#define GPP_K9 INC(GPP_K8) +#define GPP_K10 INC(GPP_K9) +#define GPP_K11 INC(GPP_K10) +#define GPP_SYS_PWROK INC(GPP_K11) +#define GPP_SYS_RESETB INC(GPP_SYS_PWROK) +#define GPP_MLK_RSTB INC(GPP_SYS_RESETB) + +/* Group F */ +#define GPP_F0 INC(GPP_MLK_RSTB) +#define GPP_F1 INC(GPP_F0) +#define GPP_F2 INC(GPP_F1) +#define GPP_F3 INC(GPP_F2) +#define GPP_F4 INC(GPP_F3) +#define GPP_F5 INC(GPP_F4) +#define GPP_F6 INC(GPP_F5) +#define GPP_F7 INC(GPP_F6) +#define GPP_F8 INC(GPP_F7) +#define GPP_F9 INC(GPP_F8) +#define GPP_F10 INC(GPP_F9) +#define GPP_F11 INC(GPP_F10) +#define GPP_F12 INC(GPP_F11) +#define GPP_F13 INC(GPP_F12) +#define GPP_F14 INC(GPP_F13) +#define GPP_F15 INC(GPP_F14) +#define GPP_F16 INC(GPP_F15) +#define GPP_F17 INC(GPP_F16) +#define GPP_F18 INC(GPP_F17) +#define GPP_F19 INC(GPP_F18) +#define GPP_F20 INC(GPP_F19) +#define GPP_F21 INC(GPP_F20) +#define GPP_F22 INC(GPP_F21) +#define GPP_F23 INC(GPP_F22) + +#define GPIO_COM4_START GPP_S0 +#define GPIO_COM4_END GPP_F23 +#define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) + +/* Group D */ +#define GPP_D0 INC(GPP_F23) +#define GPP_D1 INC(GPP_D0) +#define GPP_D2 INC(GPP_D1) +#define GPP_D3 INC(GPP_D2) +#define GPP_D4 INC(GPP_D3) +#define GPP_D5 INC(GPP_D4) +#define GPP_D6 INC(GPP_D5) +#define GPP_D7 INC(GPP_D6) +#define GPP_D8 INC(GPP_D7) +#define GPP_D9 INC(GPP_D8) +#define GPP_D10 INC(GPP_D9) +#define GPP_D11 INC(GPP_D10) +#define GPP_D12 INC(GPP_D11) +#define GPP_D13 INC(GPP_D12) +#define GPP_D14 INC(GPP_D13) +#define GPP_D15 INC(GPP_D14) +#define GPP_D16 INC(GPP_D15) +#define GPP_D17 INC(GPP_D16) +#define GPP_D18 INC(GPP_D17) +#define GPP_D19 INC(GPP_D18) +#define GPP_D20 INC(GPP_D19) +#define GPP_D21 INC(GPP_D2) +#define GPP_D22 INC(GPP_D21) +#define GPP_D23 INC(GPP_D22) +#define GPP_GSPI3_THC1_CLK_LOOPBK INC(GPP_D23) + +/* Group JTAG */ +#define GPP_JTAG_TDO INC(GPP_GSPI3_THC1_CLK_LOOPBK) +#define GPP_JTAGX INC(GPP_JTAG_TDO) +#define GPP_PRDYB INC(GPP_JTAGX) +#define GPP_PREQB INC(GPP_PRDYB) +#define GPP_JTAG_TDI INC(GPP_PREQB) +#define GPP_JTAG_TMS INC(GPP_JTAG_TDI) +#define GPP_JTAG_TCK INC(GPP_JTAG_TMS) +#define GPP_DBG_PMODE INC(GPP_JTAG_TCK) +#define GPP_CPU_TRSTB INC(GPP_DBG_PMODE) + +/* Group CPU */ +#define GPP_HDACPU_SDI INC(GPP_CPU_TRSTB) +#define GPP_HDACPU_SDO INC(GPP_HDACPU_SDI) +#define GPP_HDACPU_SCLK INC(GPP_HDACPU_SDO) +#define GPP_PM_SYNC INC(GPP_HDACPU_SCLK) +#define GPP_PECI INC(GPP_PM_SYNC) +#define GPP_CPUPWRGD INC(GPP_PECI) +#define GPP_THRMTRIPB INC(GPP_CPUPWRGD) +#define GPP_PLTRST_CPUB INC(GPP_THRMTRIPB) +#define GPP_PM_DOWN INC(GPP_PLTRST_CPUB) +#define GPP_TRIGGER_IN INC(GPP_PM_DOWN) +#define GPP_TRIGGER_OUT INC(GPP_TRIGGER_IN) +#define GPP_CLKOUT_CPURTC INC(GPP_TRIGGER_OUT) +#define GPP_VCCST_OVERRIDE INC(GPP_CLKOUT_CPURTC) +#define GPP_C10_WAKE INC(GPP_VCCST_OVERRIDE) + +#define GPIO_COM5_START GPP_D0 +#define GPIO_COM5_END GPP_C10_WAKE +#define NUM_GPIO_COM5_PADS (GPIO_COM5_END - GPIO_COM5_START + 1) + +#define TOTAL_GPIO_COMM (COMM_5 + 1) +#define TOTAL_PADS (GPIO_COM5_END + 1) + +#endif diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index 52cc0b5..da5ef28 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -106,6 +106,22 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PMC_GPP_I 0x0 +#define PMC_GPP_R 0x1 +#define PMC_GPP_J 0x2 +#define PMC_GPD 0x4 +#define PMC_GPP_D 0x5 +#define PMC_GPP_S 0x6 +#define PMC_GPP_E 0x7 +#define PMC_GPP_K 0x8 +#define PMC_GPP_F 0x9 +#define PMC_GPP_A 0xA +#define PMC_GPP_C 0xB +#define PMC_GPP_B 0xC +#define PMC_GPP_G 0xD +#define PMC_GPP_H 0xE +#else #define PMC_GPP_B 0x0 #define PMC_GPP_T 0x1 #define PMC_GPP_A 0x2 @@ -123,6 +139,7 @@ #define PMC_GPP_F 0xA #define PMC_GPP_C 0xB #define PMC_GPP_E 0xC +#endif #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index fe21b41..72717af 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -10,7 +10,7 @@ #include <fsp/util.h> #include <intelblocks/cpulib.h> #include <intelblocks/pcie_rp.h> -#include <soc/gpio_soc_defs.h> +#include <soc/gpio.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/63467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d Gerrit-Change-Number: 63467 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/denverton_ns/chip.c: add soc_acpi_name function
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60991 ) Change subject: soc/intel/denverton_ns/chip.c: add soc_acpi_name function ...................................................................... soc/intel/denverton_ns/chip.c: add soc_acpi_name function Intel common SoC code uses SoC-specific soc_acpi_name function to generate ACPI tables, add this to Denverton Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/60991 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> --- M src/soc/intel/denverton_ns/chip.c 1 file changed, 91 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mariusz Szafrański: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index c594a6f..7381b06 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -9,6 +9,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/acpi.h> #include <intelblocks/gpio.h> #include <soc/iomap.h> #include <soc/intel/common/vbt.h> @@ -18,10 +19,100 @@ #include <spi-generic.h> #include <soc/hob_mem.h> +const char *soc_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 4: return "SS01"; + case 5: return "SS02"; + case 6: return "SS03"; + case 7: return "SS04"; + } + break; + } + return NULL; + } + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: + return "MCHC"; + case PCH_DEVFN_XHCI: + return "XHCI"; + case PCH_DEVFN_UART0: + return "UAR0"; + case PCH_DEVFN_UART1: + return "UAR1"; + case PCH_DEVFN_UART2: + return "UAR2"; + case PCH_DEVFN_PCIE1: + return "RP01"; + case PCH_DEVFN_PCIE2: + return "RP02"; + case PCH_DEVFN_PCIE3: + return "RP03"; + case PCH_DEVFN_PCIE4: + return "RP04"; + case PCH_DEVFN_PCIE5: + return "RP05"; + case PCH_DEVFN_PCIE6: + return "RP06"; + case PCH_DEVFN_PCIE7: + return "RP07"; + case PCH_DEVFN_PCIE8: + return "RP08"; + case PCH_DEVFN_LPC: + return "LPCB"; + case PCH_DEVFN_SMBUS: + return "SBUS"; + case PCH_DEVFN_SATA_0: + return "SAT0"; + case PCH_DEVFN_SATA_1: + return "SAT1"; + case PCH_DEVFN_EMMC: + return "EMMC"; + case PCH_DEVFN_SPI: + return "SPI0"; + case PCH_DEVFN_PMC: + return "PMC_"; + case PCH_DEVFN_QAT: + return "QAT_"; + case PCH_DEVFN_LAN0: + return "LAN0"; + case PCH_DEVFN_LAN1: + return "LAN1"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, .scan_bus = &pci_domain_scan_bus, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif }; static struct device_operations cpu_bus_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/60991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce Gerrit-Change-Number: 60991 Gerrit-PatchSet: 14 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/denverton_ns: add common device function macros
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60990 ) Change subject: soc/intel/denverton_ns: add common device function macros ...................................................................... soc/intel/denverton_ns: add common device function macros Add device function macros for Denverton similar to other SoCs Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc Reviewed-on: https://review.coreboot.org/c/coreboot/+/60990 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> --- M src/soc/intel/denverton_ns/include/soc/pci_devs.h 1 file changed, 101 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Mariusz Szafrański: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index a337b0d..f62ea2b 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -3,19 +3,28 @@ #ifndef _DENVERTON_NS_PCI_DEVS_H_ #define _DENVERTON_NS_PCI_DEVS_H_ +#include <device/pci_def.h> + /* All these devices live on bus 0 with the associated device and function */ #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#include <device/pci_def.h> #define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func)) #else #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func) #endif /* SoC transaction router */ +#define SA_DEV_SLOT_ROOT 0x0 +#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) +#if defined(__SIMPLE_DEVICE__) +#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#else +#include <device/device.h> +#define SA_DEV_ROOT pcidev_path_on_root(PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)) +#endif #define SA_DEV 0x0 #define SA_FUNC 0 #define SOC_DEV SA_DEV @@ -26,14 +35,45 @@ #define RAS_FUNC 0 /* Root Complex Event Collector */ +#define PCH_DEV_SLOT_RCEC 0x5 +#define PCH_DEVFN_RCEC _PCH_DEVFN(RCEC, 0) +#define PCH_DEV_RCEC _PCH_DEV(RCEC, 0) #define RCEC_DEV 0x5 #define RCEC_FUNC 0 /* Virtual Root Port 2 */ +#define PCH_DEV_SLOT_QAT 0x6 +#define PCH_DEVFN_QAT _PCH_DEVFN(QAT, 0) +#define PCH_DEV_QAT _PCH_DEV(QAT, 0) #define VRP2_DEV 0x6 #define VRP2_FUNC 0 /* PCIe Root Ports */ +#define PCH_DEV_SLOT_PCIE1 0x9 +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE1, 0) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE1, 0) +#define PCH_DEV_SLOT_PCIE2 0xa +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE2, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE2, 0) +#define PCH_DEV_SLOT_PCIE3 0xb +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE3, 0) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE3, 0) +#define PCH_DEV_SLOT_PCIE4 0xc +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE4, 0) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE4, 0) +#define PCH_DEV_SLOT_PCIE5 0xe +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE5, 0) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE5, 0) +#define PCH_DEV_SLOT_PCIE6 0xf +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE6, 0) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE6, 0) +#define PCH_DEV_SLOT_PCIE7 0x10 +#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE7, 0) +#define PCH_DEV_PCIE7 _PCH_DEV(PCIE7, 0) +#define PCH_DEV_SLOT_PCIE8 0x11 +#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE8, 0) +#define PCH_DEV_PCIE8 _PCH_DEV(PCIE8, 0) + #define PCIE_DEV 0x09 #define MAX_PCIE_PORT 0x8 #define PCIE_PORT1_DEV 0x09 @@ -54,28 +94,56 @@ #define PCIE_PORT8_FUNC 0 /* SMBUS 2 */ +#define PCH_DEV_SLOT_SMBUS_HOST 0x12 +#define PCH_DEVFN_SMBUS_HOST _PCH_DEVFN(SMBUS_HOST, 0) +#define PCH_DEV_SMBUS_HOST _PCH_DEV(SMBUS_HOST, 0) #define SMBUS2_DEV 0x12 #define SMBUS2_FUNC 0 /* SATA */ +#define PCH_DEV_SLOT_SATA_0 0x13 +#define PCH_DEVFN_SATA_0 _PCH_DEVFN(SATA_0, 0) +#define PCH_DEV_SATA_0 _PCH_DEV(SATA_0, 0) +#define PCH_DEV_SLOT_SATA_1 0x14 +#define PCH_DEVFN_SATA_1 _PCH_DEVFN(SATA_1, 0) +#define PCH_DEV_SATA_1 _PCH_DEV(SATA_1, 0) #define SATA_DEV 0x13 #define SATA_FUNC 0 #define SATA2_DEV 0x14 #define SATA2_FUNC 0 /* xHCI */ +#define PCH_DEV_SLOT_XHCI 0x15 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) #define XHCI_DEV 0x15 #define XHCI_FUNC 0 /* Virtual Root Port 0 */ +#define PCH_DEV_SLOT_LAN0 0x16 +#define PCH_DEVFN_LAN0 _PCH_DEVFN(LAN0, 0) +#define PCH_DEV_LAN0 _PCH_DEV(LAN0, 0) #define VRP0_DEV 0x16 #define VRP0_FUNC 0 /* Virtual Root Port 1 */ +#define PCH_DEV_SLOT_LAN1 0x17 +#define PCH_DEVFN_LAN1 _PCH_DEVFN(LAN1, 0) +#define PCH_DEV_LAN1 _PCH_DEVFN(LAN1, 0) #define VRP1_DEV 0x17 #define VRP1_FUNC 0 /* CSME */ +#define PCH_DEV_SLOT_ME 0x18 +#define PCH_DEVFN_ME_HECI1 _PCH_DEVFN(ME, 0) +#define PCH_DEVFN_ME_HECI2 _PCH_DEVFN(ME, 1) +#define PCH_DEVFN_ME_HECI3 _PCH_DEVFN(ME, 4) +#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3) +#define PCH_DEV_ME_HECI1 _PCH_DEV(ME, 0) +#define PCH_DEV_ME_HECI2 _PCH_DEV(ME, 1) +#define PCH_DEV_ME_HECI3 _PCH_DEV(ME, 4) +#define PCH_DEV_ME_KT _PCH_DEV(ME, 3) + #define ME_HECI_DEV 0x18 #define ME_HECI1_DEV ME_HECI_DEV #define ME_HECI1_FUNC 0 @@ -89,6 +157,13 @@ #define ME_HECI3_FUNC 4 /* HSUART */ +#define PCH_DEV_SLOT_UART 0x1a +#define PCH_DEVFN_UART0 _PCH_DEVFN(UART, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(UART, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(UART, 2) +#define PCH_DEV_UART0 _PCH_DEV(UART, 0) +#define PCH_DEV_UART1 _PCH_DEV(UART, 1) +#define PCH_DEV_UART2 _PCH_DEV(UART, 2) #define HSUART_DEV 0x1a #define HSUART1_DEV HSUART_DEV #define HSUART1_FUNC 0 @@ -98,6 +173,15 @@ #define HSUART3_FUNC 2 /* IE */ +#define PCH_DEV_SLOT_IE 0x1b +#define PCH_DEVFN_IE_HECI1 _PCH_DEVFN(IE, 0) +#define PCH_DEVFN_IE_HECI2 _PCH_DEVFN(IE, 1) +#define PCH_DEVFN_IE_HECI3 _PCH_DEVFN(IE, 4) +#define PCH_DEVFN_IE_KT _PCH_DEVFN(IE, 3) +#define PCH_DEV_IE_HECI1 _PCH_DEV(IE, 0) +#define PCH_DEV_IE_HECI2 _PCH_DEV(IE, 1) +#define PCH_DEV_IE_HECI3 _PCH_DEV(IE, 4) +#define PCH_DEV_IE_KT _PCH_DEV(IE, 3) #define IE_HECI_DEV 0x1b #define IE_HECI1_DEV IE_HECI_DEV #define IE_HECI1_FUNC 0 @@ -111,10 +195,26 @@ #define IE_HECI3_FUNC 4 /* MMC Port */ +#define PCH_DEV_SLOT_EMMC 0x1c +#define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) +#define PCH_DEV_EMMC _PCH_DEV(EMMC, 0) #define MMC_DEV 0x1c #define MMC_FUNC 0 /* Platform Controller Unit */ +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) +#define PCH_DEVFN_TRACE _PCH_DEVFN(LPC, 7) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +#define PCH_DEV_PMC _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) +#define PCH_DEV_SPI _PCH_DEV(LPC, 5) +#define PCH_DEV_TRACE _PCH_DEV(LPC, 7) #define PCU_DEV 0x1f #define LPC_DEV PCU_DEV #define LPC_FUNC 0 @@ -129,25 +229,6 @@ #define NPK_DEV PCU_DEV #define NPK_FUNC 7 -/* TODO - New added */ -#define SA_DEV_SLOT_ROOT 0x00 -#define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) -#if defined(__SIMPLE_DEVICE__) -#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) -#endif - -#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) - /* VT-d support value to match FSP settings */ /* "PCH IOAPIC Config" */ #define PCH_IOAPIC_PCI_BUS 0xf0 -- To view, visit https://review.coreboot.org/c/coreboot/+/60990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc Gerrit-Change-Number: 60990 Gerrit-PatchSet: 12 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/mt8186: Disable unused power
by Felix Held (Code Review) 07 Apr '22

07 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63247 ) Change subject: soc/mediatek/mt8186: Disable unused power ...................................................................... soc/mediatek/mt8186: Disable unused power To save the power consumption, we disable the unused power of optional components in coreboot. BUG=none TEST=the value of power consumption is as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/63247 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/include/soc/spm.h M src/soc/mediatek/mt8186/spm.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index 18a9744..56e1c7a 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -836,6 +836,7 @@ check_member(mtk_spm_regs, poweron_config_set, 0x0); check_member(mtk_spm_regs, dis_pwr_con, 0x354); +check_member(mtk_spm_regs, nna_pwr_con, 0x3E0); check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c index a1186ca..30d56ff 100644 --- a/src/soc/mediatek/mt8186/spm.c +++ b/src/soc/mediatek/mt8186/spm.c @@ -362,6 +362,9 @@ ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 8) | ((pwrctrl->reg_dpmaif_ddren_req_mask_b & 0x1) << 9)); /* Auto-gen End */ + + /* Disable unused optional components */ + write32(&mtk_spm->nna_pwr_con, BIT(1) | BIT(4) | BIT(8)); } static void spm_hw_s1_state_monitor(int en) -- To view, visit https://review.coreboot.org/c/coreboot/+/63247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Gerrit-Change-Number: 63247 Gerrit-PatchSet: 9 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google,samsung: Drop init_bootmode_straps()
by Kyösti Mälkki (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Julius Werner, Angel Pons, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59008 ) Change subject: mb/google,samsung: Drop init_bootmode_straps() ...................................................................... Patch Set 3: (2 comments) File src/include/bootmode.h: https://review.coreboot.org/c/coreboot/+/59008/comment/65fd28c9_5b7d1ad1 PS2, Line 19: void stash_bootmode(int flag_spi_wp, int flag_rec_mode); > This is an old ugly hack on ancient devices that I'd prefer not to propagate to a top level API if p […] At least for samsung/lumpy, rec mode switch is momentary push button. The state was filled late in ramstage in fill_lb_gpios(). File src/mainboard/google/beltino/chromeos.c: https://review.coreboot.org/c/coreboot/+/59008/comment/468ceffb_8fb9a0cc PS3, Line 16: !get_recovery_mode_switch(), "presence"}, Does the initial state sampled late in ramstage have any significance? We're adding an actual GPIO pin and polarity here. -- To view, visit https://review.coreboot.org/c/coreboot/+/59008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Gerrit-Change-Number: 59008 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 14:30:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022