coreboot-gerrit April 2022

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Change in coreboot[master]: mb/prodrive/atlas: Update kconfig
by Lean Sheng Tan (Code Review) 07 Apr '22

07 Apr '22

Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63464 ) Change subject: mb/prodrive/atlas: Update kconfig ...................................................................... mb/prodrive/atlas: Update kconfig Update kconfig per Atlas usages. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 --- M src/mainboard/prodrive/atlas/Kconfig 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/63464/1 diff --git a/src/mainboard/prodrive/atlas/Kconfig b/src/mainboard/prodrive/atlas/Kconfig index 2faefe5..84ece41 100644 --- a/src/mainboard/prodrive/atlas/Kconfig +++ b/src/mainboard/prodrive/atlas/Kconfig @@ -1,13 +1,23 @@ config BOARD_PRODRIVE_ATLAS_BASEBOARD def_bool n + select ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_DPTF + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select DRIVERS_UART_8250IO + select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select MAINBOARD_USES_IFD_EC_REGION select SOC_INTEL_ALDERLAKE_PCH_P - + if BOARD_PRODRIVE_ATLAS_BASEBOARD +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + config MAINBOARD_FAMILY string default "PRODRIVE_ATLAS_SERIES" -- To view, visit https://review.coreboot.org/c/coreboot/+/63464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Gerrit-Change-Number: 63464 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63458 ) Change subject: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S ...................................................................... Patch Set 2: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Gerrit-Change-Number: 63458 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 13:33:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63463 to look at the new patch set (#2). Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 --- A configs/config.msi_ms7d25 A src/mainboard/msi/ms7d25/Kconfig A src/mainboard/msi/ms7d25/Kconfig.name A src/mainboard/msi/ms7d25/Makefile.inc A src/mainboard/msi/ms7d25/board_info.txt A src/mainboard/msi/ms7d25/bootblock.c A src/mainboard/msi/ms7d25/devicetree.cb A src/mainboard/msi/ms7d25/dsdt.asl A src/mainboard/msi/ms7d25/mainboard.c A src/mainboard/msi/ms7d25/romstage_fsp_params.c 10 files changed, 243 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63456 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... soc/intel/alderlake: Select FSP2.3 for ADL-S The FSP available at Intel R&DC kit #1000166 indicates FSP version 2.3 in the FSP headers. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/63456/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: superio/nuvoton/nct6687d: Add early support for NCT6687D
by Arthur Heymans (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Michał Żygowski, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63462 ) Change subject: superio/nuvoton/nct6687d: Add early support for NCT6687D ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This seems to be lacking a ramstage driver? -- To view, visit https://review.coreboot.org/c/coreboot/+/63462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e8744b5958af196de3de63de31852029d81436e Gerrit-Change-Number: 63462 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 07 Apr 2022 13:30:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63463 ) Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI ...................................................................... mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up up to romstage where it returns from FSP memory init with an error. What works: - open-source CAR setup - NCT6687D serial port with TX pin exposed on JBD1 header - SMBus reading SPD from all 4 DIMMs This board will serve as a reference board for enabling Alder Lake-S support in coreboot. More code and functionalities will be added in subsequent patches as src/soc/alderlake code will be improved for PCH-S. TEST=Extract the microcode from vendor firmware and include it in the build. The platform should print the console on the serial port even without FSP blob. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 --- A configs/config.msi_ms7d25 A src/mainboard/msi/ms7d25/Kconfig A src/mainboard/msi/ms7d25/Kconfig.name A src/mainboard/msi/ms7d25/Makefile.inc A src/mainboard/msi/ms7d25/bootblock.c A src/mainboard/msi/ms7d25/devicetree.cb A src/mainboard/msi/ms7d25/dsdt.asl A src/mainboard/msi/ms7d25/mainboard.c A src/mainboard/msi/ms7d25/romstage_fsp_params.c 9 files changed, 236 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/1 diff --git a/configs/config.msi_ms7d25 b/configs/config.msi_ms7d25 new file mode 100644 index 0000000..edcae72 --- /dev/null +++ b/configs/config.msi_ms7d25 @@ -0,0 +1,17 @@ +CONFIG_VENDOR_MSI=y +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y +CONFIG_FSP_HEADER_PATH="3rdparty/fsp/AlderLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y +CONFIG_CPU_UCODE_BINARIES="adl-s_microcode.bin" +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +CONFIG_I2C_TRANSFER_TIMEOUT_US=500000 +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_POST_DEVICE_PCI_PCIE=y +CONFIG_POST_IO_PORT=0x80 +CONFIG_SEABIOS_DEBUG_LEVEL=-1 diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig new file mode 100644 index 0000000..7411d79 --- /dev/null +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -0,0 +1,51 @@ +config BOARD_MSI_Z690_A_PRO_WIFI_DDR4 + select BOARD_MSI_MS7D25 + +config BOARD_MSI_MS7D25 + def_bool n + select SOC_INTEL_ALDERLAKE_PCH_S + select BOARD_ROMSIZE_KB_32768 + select SUPERIO_NUVOTON_NCT6776 + select DRIVERS_UART_8250IO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MAINBOARD_HAS_LPC_TPM + +if BOARD_MSI_MS7D25 + +config IGNORE_IASL_MISSING_DEPENDENCY + def_bool y + +config MAINBOARD_DIR + default "msi/ms7d25" + +config MAINBOARD_PART_NUMBER + default "PRO Z690-A WIFI DDR4(MS-7D25)" if BOARD_MSI_Z690_A_PRO_WIFI_DDR4 + +config MAINBOARD_VENDOR + string + default "Micro-Star International Co., Ltd." + +config DEVICETREE + default "devicetree.cb" + +config DIMM_SPD_SIZE + default 512 + +config UART_FOR_CONSOLE + int + default 0 + +config USE_PM_ACPI_TIMER + bool + default n + +config USE_LEGACY_8254_TIMER + bool + default n + +config CBFS_SIZE + hex + default 0x1000000 + +endif diff --git a/src/mainboard/msi/ms7d25/Kconfig.name b/src/mainboard/msi/ms7d25/Kconfig.name new file mode 100644 index 0000000..05a8cee --- /dev/null +++ b/src/mainboard/msi/ms7d25/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_Z690_A_PRO_WIFI_DDR4 + bool "PRO Z690-A WIFI DDR4" diff --git a/src/mainboard/msi/ms7d25/Makefile.inc b/src/mainboard/msi/ms7d25/Makefile.inc new file mode 100644 index 0000000..2e6759f --- /dev/null +++ b/src/mainboard/msi/ms7d25/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c new file mode 100644 index 0000000..cbadfb5 --- /dev/null +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6687d/nct6687d.h> + +#define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Replicate vendor settings for multi-function pins in global config LDN */ + nuvoton_pnp_enter_conf_state(SERIAL_DEV); + pnp_write_config(SERIAL_DEV, 0x15, 0xaa); + pnp_write_config(SERIAL_DEV, 0x1a, 0x02); + pnp_write_config(SERIAL_DEV, 0x1b, 0x02); + pnp_write_config(SERIAL_DEV, 0x1d, 0x00); + pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); + pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); + pnp_write_config(SERIAL_DEV, 0x22, 0xbd); + pnp_write_config(SERIAL_DEV, 0x23, 0xdf); + pnp_write_config(SERIAL_DEV, 0x24, 0x39); + pnp_write_config(SERIAL_DEV, 0x25, 0xfe); + pnp_write_config(SERIAL_DEV, 0x26, 0x40); + pnp_write_config(SERIAL_DEV, 0x27, 0x77); + pnp_write_config(SERIAL_DEV, 0x28, 0x00); + pnp_write_config(SERIAL_DEV, 0x29, 0xfb); + pnp_write_config(SERIAL_DEV, 0x2a, 0x80); + pnp_write_config(SERIAL_DEV, 0x2b, 0x20); + pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); + pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + nuvoton_pnp_exit_conf_state(SERIAL_DEV); + + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb new file mode 100644 index 0000000..dccaa25 --- /dev/null +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -0,0 +1,28 @@ +chip soc/intel/alderlake + device domain 0 on + device ref igpu on end + device ref crashlog off end + device ref xhci on end + device ref heci1 on end + device ref heci2 off end + device ref ide_r off end + device ref kt off end + device ref heci3 off end + device ref heci4 off end + device ref sata on end + device ref pcie_rp1 on end + device ref pcie_rp2 on end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref pcie_rp7 on end + device ref pcie_rp8 on end + device ref pcie_rp9 on end + device ref pcie_rp10 on end + device ref pcie_rp11 on end + device ref p2sb on end + device ref hda on end + device ref smbus on end + end +end diff --git a/src/mainboard/msi/ms7d25/dsdt.asl b/src/mainboard/msi/ms7d25/dsdt.asl new file mode 100644 index 0000000..d3db0e1 --- /dev/null +++ b/src/mainboard/msi/ms7d25/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> +// #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c new file mode 100644 index 0000000..ac6b252 --- /dev/null +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c new file mode 100644 index 0000000..412e3ab --- /dev/null +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistor FIXME */ + .resistor = 100, + + /* Baseboard Rcomp target values FIXME */ + .targets = { 50, 20, 25, 25, 25 }, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_DESKTOP, /* FIXME */ + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, /* FIXME */ + }, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, + }, + [1] = { + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8 Gerrit-Change-Number: 63463 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/nuvoton/nct6687d: Add early support for NCT6687D
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Felix Held. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63462 ) Change subject: superio/nuvoton/nct6687d: Add early support for NCT6687D ...................................................................... superio/nuvoton/nct6687d: Add early support for NCT6687D Based on the public datasheet of NCT6686 which should be similar to NCT6687D. TEST=Enable serial for debugging on MSI PRO Z690-A WIFI DDR4 and see coreboot console on the debug port Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0e8744b5958af196de3de63de31852029d81436e --- M src/superio/nuvoton/Makefile.inc A src/superio/nuvoton/nct6687d/Kconfig A src/superio/nuvoton/nct6687d/nct6687d.h 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/63462/1 diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index e9ac2e3..570102a 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -8,6 +8,7 @@ subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += nct5539d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d +subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776 subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d diff --git a/src/superio/nuvoton/nct6687d/Kconfig b/src/superio/nuvoton/nct6687d/Kconfig new file mode 100644 index 0000000..fecd2fe --- /dev/null +++ b/src/superio/nuvoton/nct6687d/Kconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SUPERIO_NUVOTON_NCT6687D + bool + select SUPERIO_NUVOTON_COMMON_PRE_RAM diff --git a/src/superio/nuvoton/nct6687d/nct6687d.h b/src/superio/nuvoton/nct6687d/nct6687d.h new file mode 100644 index 0000000..a9652f7 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Both NCT6687DD and NCT6687DF package variants are supported. */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_H +#define SUPERIO_NUVOTON_NCT6687D_H + +/* Logical Device Numbers (LDN). */ +#define NCT6687D_PP 0x01 /* Parallel port */ +#define NCT6687D_SP1 0x02 /* Com1 */ +#define NCT6687D_SP2 0x03 /* Com2 & IR */ +#define NCT6687D_KBC 0x05 /* PS/2 keyboard and mouse */ +#define NCT6687D_CIR 0x06 +#define NCT6687D_GPIO_0_7 0x07 /* GPIO0 - GPIO7 */ +#define NCT6687D_P80_UART 0x08 /* Port 0x 80 UART*/ +#define NCT6687D_GPIO_8_9_AF 0x09 /* GPIO8 - GPIO9, GPIO1 - GPIO8 Alternate Function */ +#define NCT6687D_ACPI 0x0A +#define NCT6687D_EC 0x0B /* EC space*/ +#define NCT6687D_RTC 0x0C +#define NCT6687D_SLEEP_PWR 0x0D /* Deep Sleep, Power Fault */ +#define NCT6687D_TACH_PWM 0x0E /* TACHIN/PWMOUT Assignment */ +#define NCT6687D_FREG 0x0F /* Function Register */ + +#endif /* SUPERIO_NUVOTON_NCT6687D_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e8744b5958af196de3de63de31852029d81436e Gerrit-Change-Number: 63462 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63461 ) Change subject: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding ...................................................................... soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding Some Super I/Os may be strapped to respond on the secondary ports 0x4e/0x4f. Enable them early so that mainboard is able to initialize a serial port for example. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a --- M src/soc/intel/alderlake/bootblock/pch.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/63461/1 diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 60f3a85..bd204cd 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -103,8 +103,8 @@ void pch_early_iorange_init(void) { - uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | - LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; + uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F | + LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; /* IO Decode Range */ if (CONFIG(DRIVERS_UART_8250IO)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6df158f54a48fb9f3173a4b209316c8116aa265a Gerrit-Change-Number: 63461 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63460 ) Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S ...................................................................... soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S According to Intel DOC #6030603 P2SB BAR must be at 0xe0000000 for PCH-S. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/63460/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 27a8fb3..c534b08 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -254,6 +254,7 @@ config PCR_BASE_ADDRESS hex + default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus. -- To view, visit https://review.coreboot.org/c/coreboot/+/63460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Gerrit-Change-Number: 63460 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63459 ) Change subject: soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces ...................................................................... soc/intel/alderlake/include/soc/iomap.h: Add ADL PCH-S reserved spaces PCH-S maps certain MMIO BARs differently than low power PCHs. The reserved ranges taken from Intel DOC #630603. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 --- M src/soc/intel/alderlake/include/soc/iomap.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/63459/1 diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 9ff8f54..4f69242 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -12,11 +12,19 @@ /* * Memory-mapped I/O registers. */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_PRESERVED_BASE_ADDRESS 0xfe000000 +#define PCH_PRESERVED_BASE_SIZE 0x00800000 + +#define PCH_TRACE_HUB_BASE_ADDRESS 0xfd800000 +#define PCH_TRACE_HUB_BASE_SIZE 0x00800000 +#else #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 #define PCH_TRACE_HUB_BASE_ADDRESS 0xfc800000 #define PCH_TRACE_HUB_BASE_SIZE 0x00800000 +#endif #define UART_BASE_SIZE 0x1000 -- To view, visit https://review.coreboot.org/c/coreboot/+/63459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefedc629def207ecd6f7be792f6e12fb6016cc3 Gerrit-Change-Number: 63459 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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