coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63458 ) Change subject: soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S ...................................................................... soc/intel/alderlake/include/soc/bootblock.h: Allow to build with PCH-S Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 --- M src/soc/intel/alderlake/include/soc/bootblock.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/63458/1 diff --git a/src/soc/intel/alderlake/include/soc/bootblock.h b/src/soc/intel/alderlake/include/soc/bootblock.h index ba4d1c2..41f99e1 100644 --- a/src/soc/intel/alderlake/include/soc/bootblock.h +++ b/src/soc/intel/alderlake/include/soc/bootblock.h @@ -5,7 +5,8 @@ #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_M) + \ CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + \ - CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) != 1 + CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) + \ + CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) != 1 #error "Please select exactly one PCH type" #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1461a8cc3c131a6e2499df8e1ebc67f5fb3b9e35 Gerrit-Change-Number: 63458 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63457 ) Change subject: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks ...................................................................... soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and CLKREQ signals. ADL-S CPUs do not have Thunderbolt. Based on the Intel DOC #619501 and #619362. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/63457/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 3608798..27a8fb3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -212,16 +212,17 @@ default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 12 if SOC_INTEL_ALDERLAKE_PCH_N default 12 if SOC_INTEL_ALDERLAKE_PCH_P + default 28 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_CPU_ROOT_PORTS int default 1 if SOC_INTEL_ALDERLAKE_PCH_M default 0 if SOC_INTEL_ALDERLAKE_PCH_N - default 3 if SOC_INTEL_ALDERLAKE_PCH_P + default 3 if SOC_INTEL_ALDERLAKE_PCH_P || SOC_INTEL_ALDERLAKE_PCH_S config MAX_TBT_ROOT_PORTS int - default 0 if SOC_INTEL_ALDERLAKE_PCH_N + default 0 if SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_ALDERLAKE_PCH_S default 2 if SOC_INTEL_ALDERLAKE_PCH_M default 4 if SOC_INTEL_ALDERLAKE_PCH_P @@ -234,12 +235,14 @@ default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 7 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config MAX_PCIE_CLOCK_REQ int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S config SMM_TSEG_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/63457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2 Gerrit-Change-Number: 63457 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63456 ) Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... soc/intel/alderlake: Select FSP2.3 for ADL-S The FSP available at Intel R&DC kit #1000166 indicates FSP version 2.3 in the FSP headers. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/63456/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a314d27..3608798 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -64,7 +64,8 @@ select MRC_SETTINGS_PROTECT select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED - select PLATFORM_USES_FSP2_2 + select PLATFORM_USES_FSP2_2 if !SOC_INTEL_ALDERLAKE_S + select PLATFORM_USES_FSP2_3 if SOC_INTEL_ALDERLAKE_S select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Introduce PCH-S symbol
by Michał Żygowski (Code Review) 07 Apr '22

07 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63455 ) Change subject: soc/intel/alderlake: Introduce PCH-S symbol ...................................................................... soc/intel/alderlake: Introduce PCH-S symbol Introduce SOC_INTEL_ALDERLAKE_PCH_S symbol to differentiate from the low power chipsets. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I47676723747458b8b7fe726e900843c198901bda --- M src/soc/intel/alderlake/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63455/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index d3c52944..a314d27 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -23,6 +23,12 @@ help Choose this option if your mainboard has a PCH-P chipset. +config SOC_INTEL_ALDERLAKE_PCH_S + bool + select SOC_INTEL_ALDERLAKE + help + Choose this option if your mainboard has a PCH-S chipset. + if SOC_INTEL_ALDERLAKE config CPU_SPECIFIC_OPTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/63455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47676723747458b8b7fe726e900843c198901bda Gerrit-Change-Number: 63455 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] Remaining ENV_ROMSTAGE cases
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63433 ) Change subject: [WIP] Remaining ENV_ROMSTAGE cases ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a1ba7ca9f5e757f062f80827d72be878e0411de Gerrit-Change-Number: 63433 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 12:55:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Philipp Hug, Michał Żygowski, ron minnich, Piotr Król. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63376 ) Change subject: [WIP] Replace some ENV_ROMSTAGE with ENV_STAGE_DOES_RAMINIT ...................................................................... Patch Set 3: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Gerrit-Change-Number: 63376 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 12:55:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by build bot (Jenkins) (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Julius Werner, Arthur Heymans, Andrey Petrov, Fred Reitberger, Yu-Ping Wu, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63375 ) Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage ...................................................................... Patch Set 5: (3 comments) File src/include/cbmem.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145737): https://review.coreboot.org/c/coreboot/+/63375/comment/42571bd6_2233f670 PS5, Line 110: #define _CBMEM_INIT_HOOK_UNUSED(init_fn_) __attribute__((unused)) \ macros should not use a trailing semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145737): https://review.coreboot.org/c/coreboot/+/63375/comment/f7a0a992_4f90db5b PS5, Line 113: #define _CBMEM_INIT_HOOK(init_fn_) \ macros should not use a trailing semicolon Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145737): https://review.coreboot.org/c/coreboot/+/63375/comment/a5334883_8041df45 PS5, Line 119: #define _CBMEM_INIT_HOOK_EARLY(init_fn_) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/63375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Gerrit-Change-Number: 63375 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 07 Apr 2022 12:55:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] CBMEM: Have INIT_HOOKS in every stage
by Kyösti Mälkki (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Hung-Te Lin, Jason Glenesk, Raul Rangel, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Julius Werner, Arthur Heymans, Andrey Petrov, Fred Reitberger, Yu-Ping Wu, Felix Held. Hello Hung-Te Lin, build bot (Jenkins), Raul Rangel, Julius Werner, Arthur Heymans, Andrey Petrov, Jason Glenesk, Marshall Dawson, Tim Wawrzynczak, Christian Walter, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63375 to look at the new patch set (#5). Change subject: [RFC] CBMEM: Have INIT_HOOKS in every stage ...................................................................... [RFC] CBMEM: Have INIT_HOOKS in every stage There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/usb/ehci_debug.c M src/drivers/vpd/vpd.c M src/include/cbmem.h M src/include/rules.h M src/lib/cbfs.c M src/lib/cbmem_console.c M src/lib/ext_stage_cache.c M src/lib/fmap.c M src/lib/imd_cbmem.c M src/lib/program.ld M src/lib/timestamp.c M src/mainboard/google/gale/mmu.c M src/mainboard/google/storm/mmu.c M src/security/tpm/tspi/log.c M src/security/vboot/common.c M src/soc/amd/common/block/pm/chipset_state.c M src/soc/amd/common/pi/heapmanager.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/quark/storage_test.c M src/soc/mediatek/common/memory.c M src/soc/qualcomm/common/qclib.c 26 files changed, 62 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/63375/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Gerrit-Change-Number: 63375 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: option: Allow to use the EFI variable driver as option backend
by Angel Pons (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Sean Rhodes, Michał Żygowski, Patrick Rudolph, Matt DeVillier. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62562 ) Change subject: option: Allow to use the EFI variable driver as option backend ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62562/comment/41a41786_431de80a PS3, Line 9: region nit: move to next line to honor the 72 character limit File src/drivers/efi/option.c: https://review.coreboot.org/c/coreboot/+/62562/comment/281520ae_e127de3f PS3, Line 42: return efi_fv_set_option(&rdev, &EficorebootNvDataGuid, name, &var, sizeof(var)); I'm somewhat concerned about returning EFI-specific error codes, even though the return value of `set_uint_option()` is currently never checked. -- To view, visit https://review.coreboot.org/c/coreboot/+/62562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Gerrit-Change-Number: 62562 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 07 Apr 2022 12:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/efi: Add EFI variable store option support
by Angel Pons (Code Review) 07 Apr '22

07 Apr '22

Attention is currently required from: Sean Rhodes, Martin Roth, Patrick Rudolph, Jakub Czapiga, Matt DeVillier, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52564 ) Change subject: drivers/efi: Add EFI variable store option support ...................................................................... Patch Set 12: Code-Review+1 (2 comments) File tests/drivers/efivars.c: https://review.coreboot.org/c/coreboot/+/52564/comment/b24a0fc7_f4572f5b PS10, Line 11: /* Firmware volume */ : 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, : 0x00, 0x00, 0x8d, 0x2b, 0xf1, 0xff, 0x96, 0x76, 0x8b, 0x4c, 0xa9, 0x85, 0x27, 0x47, : 0x07, 0x5b, 0x4f, 0x50, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5f, 0x46, : 0x56, 0x48, 0x36, 0x0e, 0x00, 0x00, 0x48, 0x00, 0x00, 0xfa, 0x00, 0x00, 0x00, 0x02, : 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, : 0x00, 0x00, : /* Variable Info Header */ : 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, : 0x77, 0x92, 0xb8, 0xff, 0x00, 0x00, 0x5a, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, : /* First entry: coreboot, data: "is great" */ : 0xaa, 0x55, 0x3f, 0xff, 0x07, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, : 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, : 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x12, 0x00, 0x00, 0x00, 0x09, 0x00, : 0x00, 0x00, 0x1d, 0x4c, 0xae, 0xce, 0x5b, 0x33, 0x85, 0x46, 0xa4, 0xa0, 0xfc, 0x4a, : 0x94, 0xee, 0xa0, 0x85, 0x63, 0x00, 0x6f, 0x00, 0x72, 0x00, 0x65, 0x00, 0x62, 0x00, : 0x6f, 0x00, 0x6f, 0x00, 0x74, 0x00, 0x00, 0x00, 0x69, 0x73, 0x20, 0x67, 0x72, 0x65, : 0x61, 0x74, 0x00, > nit: Can you make it more descriptive? I guess one could use a struct, but it might cause endianness issues. File tests/drivers/efivars.c: https://review.coreboot.org/c/coreboot/+/52564/comment/5709fdeb_884cc4a5 PS12, Line 117: "is awesome" Idea: store this in an array to avoid repeating it four times? -- To view, visit https://review.coreboot.org/c/coreboot/+/52564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Gerrit-Change-Number: 52564 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 07 Apr 2022 12:21:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: comment

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