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Change subject: soc/intel/alderlake: Introduce PCH-S symbol
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63455/comment/d63277b6_0f42a3e8
PS1, Line 26: config SOC_INTEL_ALDERLAKE_PCH_S
> You'd also need to adjust the check in src/soc/intel/alderlake/include/soc/bootblock. […]
Done in CB:63458
Currently no board selects this option, so no harm.
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Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
......................................................................
Patch Set 4: Verified+1
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Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans, Lean Sheng Tan, Eric Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63167
to look at the new patch set (#6).
Change subject: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
......................................................................
soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
This patch binds all FSP-M and FSP-S UPDs required for serial
redirection with `FSP_ENABLE_SERIAL_DEBUG` config to allow coreboot to
choose when to enable FSP debug output redirection to serial port.
For example:
PcdSerialDebugLevel => For controlling FSP debug level between FSP-M/S
SerialDebugMrcLevel => For controllig MRC debug level.
With this change FSP debug output will only be enabled when the user
enables `FSP_ENABLE_SERIAL_DEBUG` from site-local config with coreboot
serial image.
BUG=b:225544587
TEST=Able to build and boot brya. Also, the FSP debug log is exactly
the same before and with this code change.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 20 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63167/6
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Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63467 )
Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h:
https://review.coreboot.org/c/coreboot/+/63467/comment/0ab05dd3_aa6e8423
PS1, Line 288: #define GPP_F20_IRQ 0x70
: #define GPP_F21_IRQ 0x71
: #define GPP_F22_IRQ 0x72
: #define GPP_F23_IRQ 0x73
:
: /* Group D */
: #define GPP_D0_IRQ 0x70
: #define GPP_D1_IRQ 0x71
: #define GPP_D2_IRQ 0x72
: #define GPP_D3_IRQ 0x73
> is this really the way they overlap, seems odd, would expect it to start over from 0x18 like D8 does […]
hmm, that's what doc #621483 says
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Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/63167/comment/00928e27_f0d2c306
PS5, Line 513: if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER)) {
: if (CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG))
nit: logic is the same as
```
if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && CONFIG(FSP_ENABLE_SERIAL_DEBUG))
```
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Change subject: drivers/intel/fsp2_0: Allow coreboot to control FSP serial redirection
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/alderlake: Introduce PCH-S symbol
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63455/comment/a7736b1d_fe1e4cb5
PS1, Line 26: config SOC_INTEL_ALDERLAKE_PCH_S
You'd also need to adjust the check in src/soc/intel/alderlake/include/soc/bootblock.h to account for this option.
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Change subject: mb/prodrive/atlas: Disable ASPM for i225 port
......................................................................
Patch Set 3: Code-Review+2
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