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Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h:
https://review.coreboot.org/c/coreboot/+/63467/comment/ad1a3f2b_ae8a0fe3
PS1, Line 288: #define GPP_F20_IRQ 0x70
: #define GPP_F21_IRQ 0x71
: #define GPP_F22_IRQ 0x72
: #define GPP_F23_IRQ 0x73
:
: /* Group D */
: #define GPP_D0_IRQ 0x70
: #define GPP_D1_IRQ 0x71
: #define GPP_D2_IRQ 0x72
: #define GPP_D3_IRQ 0x73
is this really the way they overlap, seems odd, would expect it to start over from 0x18 like D8 does...
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Change subject: mb/prodrive/atlas: Update GPIOs
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/prodrive/atlas/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/63411/comment/a34f7db5_ddb0e7bb
PS1, Line 14: EC_IN_RW
> Isn't this signal `EC_SMI_N` as per schematics? Or has it been repurposed?
yes correct it is EC_SMI_N, which is the same as RVP. but RVP name it as EC_IN_RW I think to reflect the purpose accurately?
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Change subject: mb/prodrive/atlas: Update GPIOs
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/prodrive/atlas/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/63411/comment/1dbf9051_269f083b
PS1, Line 14: EC_IN_RW
Isn't this signal `EC_SMI_N` as per schematics? Or has it been repurposed?
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Change subject: mb/prodrive/atlas: Update GPIOs
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/sabrina: Build support to add SPL File
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/sabrina/Kconfig:
https://review.coreboot.org/c/coreboot/+/63313/comment/18a433b3_87f8dfda
PS1, Line 394: Have a mainboard specific SPL table file, which is created by AMD
would be good to mention that this is an override of the default one in amd_blobs
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Change subject: mb/prodrive/atlas: Update correct SPD address
......................................................................
Patch Set 1: Code-Review+2
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Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62776 )
Change subject: mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
......................................................................
mb/google/dedede/var/beadrix: Update PCIe and SATA pins for low power consumption
To achieve low power consumption, we disable unused PCIe and SATA
pins at beadrix/overridetree.cb according to baseboard/devicetree.cb
and mainboard schematic. Original measured beadrix board's power
consumption is about 250 mW. After we disable unused PCIe and SATA
pins, as well as, enable the other low power MUX CL (3487086: USB
MUX: Update low power mode of MUX anx7447 used as MUX only |
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/
+/3487086), the measured power consumption achieves about 110 ~ 116
mW, as well as, meets Google battery life for 14 days in the suspend
state and Intel low power consumption about 116 mW.
BRANCH=dedede
BUG=b:204882915
TEST=on beadrix, measured power consumption meets Intel power
consumption.
Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com>
Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776
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---
M src/mainboard/google/dedede/variants/beadrix/overridetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Karthik Ramasubramanian: Looks good to me, approved
Super Ni: Looks good to me, but someone else must approve
Teddy Shih: Looks good to me, but someone else must approve
Teddy Shih: Looks good to me, but someone else must approve
Ivan Chen: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
index d5b37d4..8a12e41 100644
--- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb
@@ -1,7 +1,9 @@
chip soc/intel/jasperlake
# USB Port Configuration
+ register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable unused USB2P_5 and USB2N_5
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable unused USB2P_7 and USB2N_7
# Intel Common SoC Config
#+-------------------+---------------------------+
@@ -115,6 +117,7 @@
device i2c 15 on end
end
end # I2C 0
+ device pci 17.0 off end # SATA. Baseboard/devicetree.cb is off
device pci 19.0 on
chip drivers/i2c/generic
register "hid" = ""10EC5682""
@@ -128,6 +131,8 @@
device i2c 1a on end
end
end # I2C 4
+ device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off
+ device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1
device pci 1f.3 on
chip drivers/generic/max98357a
register "hid" = ""MX98360A""
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Change subject: soc/intel/alderlake/bootblock/pch.c: Enable SIO 4e/4f ports decoding
......................................................................
Patch Set 2: Code-Review+2
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