coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski, Maxim Polyakov, Angel Pons. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake macro generation ...................................................................... Patch Set 4: (1 comment) File util/intelp2m/platforms/adl/macro.go: https://review.coreboot.org/c/coreboot/+/63403/comment/fc8935dd_045acafd PS4, Line 52: var remapping = map[uint8]uint32{ > This doesn't match what is done in CB:63467 […] According to doc #621483, this is correct, and CB:63467 is wrong. Will fix -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:34:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63493 ) Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... Patch Set 2: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63493/comment/fce60377_38655a5e PS1, Line 11: 619015 > Did you mean 619501 ADL processors EDS? Sure did. Done File src/soc/intel/alderlake/chipset_pch_s.cb: https://review.coreboot.org/c/coreboot/+/63493/comment/41f25a4e_c1fccaeb PS1, Line 4: > Missing power limits. PL1 PL2 DOC #619501 Table 15 and 19 […] Added power limits as per doc https://review.coreboot.org/c/coreboot/+/63493/comment/298dc62d_42d00ec0 PS1, Line 12: device pci 05.0 alias ipu off end > Not present on PCH-S Done https://review.coreboot.org/c/coreboot/+/63493/comment/a34d13c6_279fd646 PS1, Line 14: device pci 06.2 alias pcie4_1 off end > If we talk about ADL-S CPU only, it does not contain PCIe 6.2 (only H, P and U15 lines do). Done https://review.coreboot.org/c/coreboot/+/63493/comment/aa88b9a6_ec2fb2fb PS1, Line 19: device pci 12.0 alias ish off end > pci 11. […] Done https://review.coreboot.org/c/coreboot/+/63493/comment/0b463d73_c7f4e1fe PS1, Line 25: device usb 0.0 alias xhci_root_hub off : chip drivers/usb/acpi : device usb 2.0 alias usb2_port1 off end : end : chip drivers/usb/acpi : device usb 2.1 alias usb2_port2 off end : end : chip drivers/usb/acpi : device usb 2.2 alias usb2_port3 off end : end : chip drivers/usb/acpi : device usb 2.3 alias usb2_port4 off end : end : chip drivers/usb/acpi : device usb 2.4 alias usb2_port5 off end : end : chip drivers/usb/acpi : device usb 2.5 alias usb2_port6 off end : end : chip drivers/usb/acpi : device usb 2.6 alias usb2_port7 off end : end : chip drivers/usb/acpi : device usb 2.7 alias usb2_port8 off end : end : chip drivers/usb/acpi : device usb 2.8 alias usb2_port9 off end : end : chip drivers/usb/acpi : device usb 2.9 alias usb2_port10 off end : end : chip drivers/usb/acpi : device usb 3.0 alias usb3_port1 off end : end : chip drivers/usb/acpi : device usb 3.1 alias usb3_port2 off end : end : chip drivers/usb/acpi : device usb 3.2 alias usb3_port3 off end : end : chip drivers/usb/acpi : device usb 3.3 alias usb3_port4 off end : end : end > 10 USB 3.x ports and 14 USB2. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:17:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Kopeć (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć, Tim Wawrzynczak. Hello Michał Żygowski, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63493 to look at the new patch set (#2). Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... soc/intel/alderlake: add chipset devicetree for ADL-S Add chipset devicetree and power limits for AlderLake-S platform. Based on Intel docs #619501 and #619362. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h A src/soc/intel/alderlake/chipset_pch_s.cb 3 files changed, 205 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63493/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Maxim Polyakov, Michał Kopeć, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake macro generation ...................................................................... Patch Set 4: (1 comment) File util/intelp2m/platforms/adl/macro.go: https://review.coreboot.org/c/coreboot/+/63403/comment/f1b8dab6_7bb945a4 PS4, Line 52: var remapping = map[uint8]uint32{ This doesn't match what is done in CB:63467 static const struct reset_mapping rst_map_gpp[] = { { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 }, { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 }, { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 }, }; Or I don't understand something here? -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 12:11:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller
by Angel Pons (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Kangheui Won, Paul Menzel, Tim Wawrzynczak, Rizwan Qureshi, Meera Ravindranath, Usha P, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 ) Change subject: soc/intel/alderlake: Add support for UFS controller ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62856/comment/4d91b186_76738a40 PS7, Line 15: 2) Hook up FSP enable UPD for UFS #1 to the device from chipset.cb > Why can’t coreboot enable this controller? Or is it just to make the PCIe(?) device visible? FSP doesn't just enable the PCI device, it also performs some initialization steps. Anything to do? -- To view, visit https://review.coreboot.org/c/coreboot/+/62856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92f024ded64e1eaef41a7807133361d74b5009d4 Gerrit-Change-Number: 62856 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:51:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/smm_module_load: Rewrite setup_stub
by Krystian Hebel (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Arthur Heymans. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63478 ) Change subject: cpu/x86/smm_module_load: Rewrite setup_stub ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63478/comment/ed903739_35315142 PS4, Line 14: effectively fixes SMM on all but CPU0! This may be poorly worded. Without context, one can read it as "CPU0 is still affected" -- To view, visit https://review.coreboot.org/c/coreboot/+/63478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ef9d6a30f3039f25e2cde975086a1365ca4182 Gerrit-Change-Number: 63478 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:37:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Taniya Das (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Shelley Chen, Taniya Das, Paul Menzel, Julius Werner. Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: LGTM. -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:36:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Kyösti Mälkki (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Raul Rangel, Nico Huber, Xiang W, Philipp Hug, Jonathan Neuschäfer, Tim Wawrzynczak, Angel Pons, Rob Barnes, Karthik Ramasubramanian. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: > > All this review is happening in a no-op change, while CB:59321 is where spinlock/mutex change real […] You can have your size comparison of the two approaches, but for that I need a commit hash for Raul's work rebased on master. I anticipate PCI IO config to blow if we make it SMP safe with mutex. I have still not seen comments or numbers what happens to DMA performance if console loglevel changes or UART8250MEM has not been selected. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 15 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:27:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d5: add GPIO configuration
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63490 ) Change subject: mb/msi/ms7d5: add GPIO configuration ...................................................................... Patch Set 2: (1 comment) File src/mainboard/msi/ms7d25/mainboard.c: https://review.coreboot.org/c/coreboot/+/63490/comment/66a98dfe_dec6795e PS2, Line 8: gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); This should be called in the mainboard_silicon_init_params right before FSP silicon init. -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:17:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Maxim Polyakov, Michał Kopeć, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake macro generation ...................................................................... Patch Set 4: (1 comment) File util/intelp2m/platforms/adlh/macro.go: https://review.coreboot.org/c/coreboot/+/63403/comment/bfbc5a3c_9cd897c5 PS2, Line 20: MAX_DW_NUM = common.MAX_DW_NUM > They aren't. Here's a sample of inteltool output: […] ADL PCH-H EDS describes only DW0 and DW1. -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 11:14:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022