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Change subject: util/intelp2m: Add support for Alder Lake macro generation
......................................................................
Patch Set 4:
(1 comment)
File util/intelp2m/parser/parser.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/eb36233f_0b7cbadf
PS4, Line 152: cnl.PlatformSpecific{}
snr.PlatformSpecific{} in the previous patch was right
An interface in go is a pointer that will be null if you don't initialize it.
If so, we have an attempt to dereference a null pointer here -
https://github.com/coreboot/coreboot/blob/master/util/intelp2m/platforms/cn…
and here
https://github.com/coreboot/coreboot/blob/master/util/intelp2m/platforms/cn…
The PlatformSpecific structure for the "cnl" package includes two such pointers, one of which you initialized in util/intelp2m/platforms/adl/macro.go. The second interface for reusing KeywordCheck() is initialized here
config.AlderType: adl.PlatformSpecific{
InheritanceTemplate: cnl.PlatformSpecific{
InheritanceTemplate: snr.PlatformSpecific{},
},
},
But this makes no sense, since both "cnl" and "snr" use the same KeywordCheck() function. Therefore, for the cleanliness of the code, we use KeywordCheck() from the "snr" package.
config.AlderType: adl.PlatformSpecific{
InheritanceTemplate: snr.PlatformSpecific{},
},
snr.PlatformSpecific{} doesn't have these interfaces, because it does not use code from another platform - https://github.com/coreboot/coreboot/blob/master/util/intelp2m/platforms/sn…
intelp2m$ make
go version
go version go1.18 linux/amd64
GO111MODULE=off go build -v -o intelp2m
intelp2m$ ./intelp2m -file inteltool-examples/inteltool-adl.log -iiii -fld cb -p adl -o gpio_adl_h.h
Info level: Use level 4!
Log file: inteltool-examples/inteltool-adl.log
Output generated file: gpio_adl_h.h
Parse IntelTool Log File...
...done!
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Change subject: libpayload/defconfig: enable vboot Lib Build
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63240/comment/4a84a9e7_df3edea1
PS3, Line 9: #3461454
> > Does it mean CONFIG_LP_CHROMEOS=y has to be set in depthcharge board/<BOARD>/defconfig ? […]
Thank you for the clarification.
In this case the alternative is to create a board specific defconfig in coreboot/payloads/libpayload/configs/config.<BOARD> and set CONFIG_LP_DEFCONFIG_OVERRIDE=n for coreboot build. This however means we need to duplicate the config.<BOARD> for every other chrome board.
Another alternative is to introduce another Kconfig in depthcharge and let it pick a config.chromeos
Is that a right understanding ?
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Change subject: console/ehci_debug: Move driver to own compilation unit
......................................................................
Patch Set 13: Verified+1
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Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
Patch Set 8:
(9 comments)
File util/inteltool/gpio_names/alderlake_h.h:
https://review.coreboot.org/c/coreboot/+/63374/comment/0ecf82ce_4d843667
PS8, Line 102: const char *const alderlake_pch_h_group_d_names[] = {
The DOC #618659 has copy-pasta error, the NF6 column should obviously contain:
`USB_C_GPP_Dx` not `USB_C_GPP_Cx`
https://review.coreboot.org/c/coreboot/+/63374/comment/4ca34220_87d2ffdb
PS8, Line 437: &alderlake_pch_h_group_j,
In the coreboot tree we add vgpios, for completeness we should add them here as well
https://review.coreboot.org/c/coreboot/+/63374/comment/76f56091_e23e05c3
PS8, Line 473: &alderlake_pch_h_group_c,
vpgio3 missing
https://review.coreboot.org/c/coreboot/+/63374/comment/d82e1759_f070a9d6
PS8, Line 498: &alderlake_pch_h_group_d,
jtag and cpu gorups missing
File util/inteltool/inteltool.h:
https://review.coreboot.org/c/coreboot/+/63374/comment/ae852334_aa3359b1
PS8, Line 356: #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_H_6_8 0x4641 /* Alderlake H 6+8 */
This is H processor line, different from S and HX line which the dump/patch is for.
https://review.coreboot.org/c/coreboot/+/63374/comment/0f572e35_6c456363
PS8, Line 436: #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
There are more IDs based on the stepping for S LGA and HX SBGA
https://review.coreboot.org/c/coreboot/+/63374/comment/a53b9335_60ac1853
PS8, Line 437: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0
: #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
Not an ADL-S/HX GT devices
File util/inteltool/inteltool.c:
https://review.coreboot.org/c/coreboot/+/63374/comment/b08069fd_08986eeb
PS8, Line 173: { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_H_6_8,
: "12th generation (Alder Lake H family) Core Processor (Mobile)" },
Not an ADL-S/HX line
https://review.coreboot.org/c/coreboot/+/63374/comment/19a54b3c_cc0a9e3e
PS8, Line 545: { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_P_GT2,
: "Intel(R) AlderLake-P GT2" },
: { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_M_GT1,
: "Intel(R) AlderLake-M GT1" },
Not an ADL-S/HX GT devices
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Change subject: drivers/spkmodem: Move the driver to proper compilation unit
......................................................................
Patch Set 13: Verified+1
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I'd like you to reexamine a change. Please visit
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Change subject: console/cbmemc: Move to own compilation unit
......................................................................
console/cbmemc: Move to own compilation unit
Change-Id: Iffa4e90243c9fb4dbb17364e0ff2518764a7e9f1
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/console/Makefile.inc
D src/console/hw_consoles.c
M src/lib/cbmem_console.c
3 files changed, 8 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/56484/15
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Change subject: console/uart: Move driver to own compilation unit
......................................................................
console/uart: Move driver to own compilation unit
Change-Id: Ife70c603c99963425331542970d02283dc608f59
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/console/Makefile.inc
M src/console/hw_consoles.c
A src/console/uart.c
M src/include/console/uart.h
4 files changed, 43 insertions(+), 26 deletions(-)
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Change subject: console/flashconsole: Move driver to own compilation unit
......................................................................
console/flashconsole: Move driver to own compilation unit
Change-Id: I4360e6bbe161945ecc74f06e9f8b8e9efa88b0cb
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/console/hw_consoles.c
M src/drivers/spi/flashconsole.c
D src/include/console/flash.h
3 files changed, 16 insertions(+), 31 deletions(-)
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Change subject: lib/console: Use a linkerscript array for console drivers
......................................................................
lib/console: Use a linkerscript array for console drivers
Now all init/tx/tx_flush calls are used as function pointers inside
hw_consoles.c. The idea of this patch is to add the ability link in
console drivers. This for instance makes using multiple uarts easier.
rx calls are for pretty specific use cases so it make sense not to
handle those in the console driver for now.
Change-Id: Ib2468e03fba087a4fc43e6365856030e4c7f1cea
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/console/Makefile.inc
M src/console/console.c
A src/console/hw_consoles.c
M src/console/printk.c
M src/include/console/cbmem_console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/streams.h
M src/include/console/system76_ec.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/lib/Makefile.inc
M src/lib/program.ld
M src/soc/amd/common/psp_verstage/printk.c
M src/soc/qualcomm/common/qclib.c
18 files changed, 172 insertions(+), 135 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/56472/17
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Igor Bagnucki has uploaded a new patch set (#4) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/63463 )
Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
......................................................................
mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up
up to romstage where it returns from FSP memory init with an error.
What works:
- open-source CAR setup
- NCT6687D serial port with TX pin exposed on JBD1 header
- SMBus reading SPD from all 4 DIMMs
This board will serve as a reference board for enabling Alder Lake-S
support in coreboot. More code and functionalities will be added in
subsequent patches as src/soc/alderlake code will be improved for
PCH-S.
TEST=Extract the microcode from vendor firmware and include it in the
build. The platform should print the console on the serial port even
without FSP blob.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8
Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com>
---
A configs/config.msi_ms7d25
A src/mainboard/msi/ms7d25/Kconfig
A src/mainboard/msi/ms7d25/Kconfig.name
A src/mainboard/msi/ms7d25/Makefile.inc
A src/mainboard/msi/ms7d25/board_info.txt
A src/mainboard/msi/ms7d25/bootblock.c
A src/mainboard/msi/ms7d25/devicetree.cb
A src/mainboard/msi/ms7d25/dsdt.asl
A src/mainboard/msi/ms7d25/mainboard.c
A src/mainboard/msi/ms7d25/romstage_fsp_params.c
10 files changed, 245 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/4
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Attention: Igor Bagnucki <igor.bagnucki(a)3mdeb.com>
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