coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Tim Wawrzynczak (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Sridhar Siricilla, Angel Pons, Kane Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 7: Code-Review+1 (2 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/63293/comment/2eb27e66_77c05ca1 PS7, Line 578: * Add Workaround to disable PCH USB2 Phy power gating as per Intel TA# 723158 to : * prevent possible display flicker issue. : * Enable or Disable PCH USB2 Phy power gating. : * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. I would add this comment into the mainboard patch, not the SoC code; there could be other valid reasons for this setting this option, unrelated to the TA ? https://review.coreboot.org/c/coreboot/+/63293/comment/0566d59c_a09c3cba PS7, Line 582: * nit; extra blank line -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:05:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG
by Lean Sheng Tan (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Arthur Heymans, Nick Vaccaro. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63167 ) Change subject: soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I779c56b8b0fdebf45ea85b3b456a2d8066e26489 Gerrit-Change-Number: 63167 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:02:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Raul Rangel (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Nico Huber, Xiang W, Philipp Hug, Jonathan Neuschäfer, Tim Wawrzynczak, Angel Pons, Kyösti Mälkki, Rob Barnes, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: > You can have your size comparison of the two approaches, but for that I need a commit hash for Raul' […] DMA performance doesn't depend on UART or log level. Each DMA transaction takes anywhere from 8-10ms, so we don't need to poll it constantly. As for numbers, the rest of the patch train has them. I can rework the patch train sometime next week. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 15 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 14:56:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mb/facebook/fbg1701: Verify FSP and SPD binaries in bootblock
by Felix Held (Code Review) 08 Apr '22

08 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63446 ) Change subject: src/mb/facebook/fbg1701: Verify FSP and SPD binaries in bootblock ...................................................................... src/mb/facebook/fbg1701: Verify FSP and SPD binaries in bootblock romstage uses FSP and SPD before these are verified. Verify the FSP and SPD binaries in bootblock and measure these in romstage. BUG=N/A TEST=Boot Facebook FBG1701 and check log for FSP and SPD verified in bootblock. Change-Id: I061affa5111fb14d69a8459575e0c72f71b1a1aa Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63446 Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/facebook/fbg1701/board_verified_boot.c 1 file changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 5fbcf2c..8b644cb 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -2,7 +2,8 @@ #include "board_verified_boot.h" -/* The items verified by the bootblock, the bootblock will not measure the +/* + * The items verified by the bootblock, the bootblock will not measure the * items to the TPM */ const verify_item_t bootblock_verify_list[] = { @@ -10,6 +11,10 @@ HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 }, { VERIFY_FILE, BOOTBLOCK, { { NULL, CBFS_TYPE_BOOTBLOCK } }, HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, + { VERIFY_FILE, FSP, { { NULL, CBFS_TYPE_FSP } }, HASH_IDX_FSP, + MBOOT_PCR_INDEX_1 }, + { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, + HASH_IDX_SPD0, MBOOT_PCR_INDEX_1 }, #if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) { VERIFY_BLOCK, "PublicKey", { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, @@ -20,7 +25,7 @@ }; /* - * The items used by the romstage. Bootblock and PublicKey are added here to make sure they + * The items used by the romstage. Items verified by bootblock are added here to make sure they * are measured */ const verify_item_t romstage_verify_list[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I061affa5111fb14d69a8459575e0c72f71b1a1aa Gerrit-Change-Number: 63446 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: IASL: Correct warning message for IASL missing dependency
by Felix Held (Code Review) 08 Apr '22

08 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63250 ) Change subject: IASL: Correct warning message for IASL missing dependency ...................................................................... IASL: Correct warning message for IASL missing dependency Warning for _SRS includes _SRS. Warning for _DIS includes must have _SRS twice. Remove requirement _SRS for _SRS is present. Removed second _SRS for _DIS is present. BUG=N/A TEST=Verify correct message on built of facebook FBG1701 Change-Id: I1be740354b159e931e41323aef14e160cc09af19 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>´ Reviewed-on: https://review.coreboot.org/c/coreboot/+/63250 Reviewed-by: Erik van den Bogaert <ebogaert(a)eltan.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Erik van den Bogaert: Looks good to me, but someone else must approve diff --git a/Makefile.inc b/Makefile.inc index f746ef9..6b1c45c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -277,8 +277,8 @@ build_complete:: printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n" printf "*** If _PRS is present, must have _CRS and _SRS ***\n" - printf "*** If _SRS is present, must have _PRS, _CRS, and _SRS ***\n" - printf "*** If _DIS is present, must have _SRS, _PRS, _CRS, and _SRS ***\n" + printf "*** If _SRS is present, must have _PRS and _CRS ***\n" + printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n" endif IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be740354b159e931e41323aef14e160cc09af19 Gerrit-Change-Number: 63250 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter
by Felix Held (Code Review) 08 Apr '22

08 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62889 ) Change subject: soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter ...................................................................... soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter Commit 1a4496e79f21 (soc/{apl,glk}: Allow to select the primary graphics device) adds code to set the FSP parameter 'PrimaryVideoAdaptor' based on the enum description of the FspmUpd.h for Apollo Lake. Unfortunately, the comment in the header file does not match the implementation in the FSP and hence setting PrimaryVideoAdaptor to 'GPU_PRIMARY_IGD' will be treated as if the selection was 'GPU_PRIMARY_PCI'. This in turn leads to Linux gfx driver issues for earlier driver implementations. This commit corrects the enum values for the FSP parameter to match the implementation. TEST=Boot into Linux on mc_apl1 and verify that graphics works. Change-Id: Iedbc144fa809f6d4587f5223b235ee95579c48f7 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62889 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Maxim Polyakov: Looks good to me, approved diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 08543b1..1d8752f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -232,8 +232,8 @@ static void soc_gpu_init_params(FSPM_UPD *mupd) { enum { - GPU_PRIMARY_IGD = 2, - GPU_PRIMARY_PCI = 3, + GPU_PRIMARY_IGD = 0, + GPU_PRIMARY_PCI = 1, }; /* Select primary GPU device */ if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && is_devfn_enabled(SA_DEVFN_IGD)) -- To view, visit https://review.coreboot.org/c/coreboot/+/62889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedbc144fa809f6d4587f5223b235ee95579c48f7 Gerrit-Change-Number: 62889 Gerrit-PatchSet: 3 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG
by Arthur Heymans (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Kyösti Mälkki. Arthur Heymans has uploaded a new patch set (#8) to the change originally created by Kyösti Mälkki. ( https://review.coreboot.org/c/coreboot/+/61494 ) Change subject: mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG ...................................................................... mb/emulation/qemu-q35: Support PARALLEL_MP with SMM_ASEG Tested with SMI_DEBUG: SMM prints things on the console. Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/qemu-x86/Kconfig M src/include/cpu/intel/smm_reloc.h M src/mainboard/emulation/qemu-i440fx/northbridge.c M src/mainboard/emulation/qemu-q35/cpu.c M src/mainboard/emulation/qemu-q35/memmap.c 5 files changed, 18 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/61494/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13 Gerrit-Change-Number: 61494 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Show CSE device slot and function number properly
by Felix Held (Code Review) 08 Apr '22

08 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63406 ) Change subject: soc/intel/common/cse: Show CSE device slot and function number properly ...................................................................... soc/intel/common/cse: Show CSE device slot and function number properly This patch fixes a problem where the `is_cse_devfn_visible` function is unable to show the CSE device slot and function number properly. BUG=b:211954778 TEST=Able to display CSE device slot and function number properly as below: Before: [DEBUG] PCI: 00:16.0 final [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled [WARN ] HECI: CSE device 00.0 is disabled With this code changes: [DEBUG] PCI: 00:16.0 final [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63406 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 32b7f20..2444cee 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1012,11 +1012,11 @@ void heci_set_to_d0i3(void) { for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { - pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEV_SLOT_CSE), PCI_FUNC(i)); - if (!is_cse_devfn_visible(dev)) + pci_devfn_t devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); + if (!is_cse_devfn_visible(devfn)) continue; - set_cse_device_state(dev, DEV_IDLE); + set_cse_device_state(devfn, DEV_IDLE); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76a634c64af26fc0ac24e2c0bb3a8f397a65d77b Gerrit-Change-Number: 63406 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cse: Allow calling all functions associated with `cse_final`
by Felix Held (Code Review) 08 Apr '22

08 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63405 ) Change subject: soc/intel/cse: Allow calling all functions associated with `cse_final` ...................................................................... soc/intel/cse: Allow calling all functions associated with `cse_final` This patch fixes a problem where `cse_final` only calls into 1 function from available `notify_func` lists. BUG=b:211954778 TEST=Able to execute `cse_final_end_of_firmware` function as part of `cse_final` call. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63405 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d786a65..32b7f20 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1254,7 +1254,7 @@ { for (size_t i = 0; i < ARRAY_SIZE(notify_data); i++) { if (!notify_data[i].skip) - return notify_data[i].notify_func(); + notify_data[i].notify_func(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04d8c9c1213ddeb9ed85473e62fcca298c0d5172 Gerrit-Change-Number: 63405 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
by Eric Lai (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Amanda Hwang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63495 ) Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/brya0/fw_config.c: https://review.coreboot.org/c/coreboot/+/63495/comment/19c7d3e4_61599f6c PS3, Line 143: if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { since I2S0 not used here, you can i2s0_disable_pads -- To view, visit https://review.coreboot.org/c/coreboot/+/63495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4 Gerrit-Change-Number: 63495 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 14:40:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2022