coreboot-gerrit April 2022

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Change in coreboot[master]: [Brya] [Debug] src/mb/brya: Disable GPIO register locking for GPP_F17
by Anil Kumar K (Code Review) 08 Apr '22

08 Apr '22

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63506 ) Change subject: [Brya] [Debug] src/mb/brya: Disable GPIO register locking for GPP_F17 ...................................................................... [Brya] [Debug] src/mb/brya: Disable GPIO register locking for GPP_F17 Change-Id: Ie61f7144538f3443df19eb02fe420979f3886247 --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/63506/1 diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index fb7bc21..ac0fd4d 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -246,7 +246,8 @@ /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie61f7144538f3443df19eb02fe420979f3886247 Gerrit-Change-Number: 63506 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelp2m: Add support for Alder Lake macro generation
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Maxim Polyakov, Michał Kopeć, Angel Pons. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63403 ) Change subject: util/intelp2m: Add support for Alder Lake macro generation ...................................................................... Patch Set 5: (1 comment) File util/intelp2m/platforms/adl/macro.go: https://review.coreboot.org/c/coreboot/+/63403/comment/a28a34a0_3e7ce7f6 PS4, Line 52: var remapping = map[uint8]uint32{ > Done I can see the following reset configs for GPP_I for example: 00b - Global Reset or RSMRST# 01b - Host Deep Reset 10b - PLTRST# 11b - Global Reset We do not map the 4th one? -- To view, visit https://review.coreboot.org/c/coreboot/+/63403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5871394bcb0636c2c803607ffb129441aa934417 Gerrit-Change-Number: 63403 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 16:38:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [brya][Debug] src/mb/brya: Disable GPIO PM for all variants
by build bot (Jenkins) (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63505 ) Change subject: [brya][Debug] src/mb/brya: Disable GPIO PM for all variants ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145927): https://review.coreboot.org/c/coreboot/+/63505/comment/bda41d75_ef098413 PS1, Line 59: /* [Debug] disable GPIO PM unconditionally */ trailing whitespace -- To view, visit https://review.coreboot.org/c/coreboot/+/63505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac5f13f65fd1cf6281e1d05fef1219236ba2c51 Gerrit-Change-Number: 63505 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 16:30:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [brya][Debug] src/mb/brya: Disable GPIO PM for all variants
by Anil Kumar K (Code Review) 08 Apr '22

08 Apr '22

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63505 ) Change subject: [brya][Debug] src/mb/brya: Disable GPIO PM for all variants ...................................................................... [brya][Debug] src/mb/brya: Disable GPIO PM for all variants Change-Id: I5ac5f13f65fd1cf6281e1d05fef1219236ba2c51 --- M src/mainboard/google/brya/mainboard.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/63505/1 diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index b3f42ca..8253db8f 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -56,6 +56,15 @@ config->gpio_pm[COMM_5] = 0; } + /* [Debug] disable GPIO PM unconditionally */ + config->gpio_override_pm = 1; + config->gpio_pm[COMM_0] = 0; + config->gpio_pm[COMM_1] = 0; + config->gpio_pm[COMM_2] = 0; + config->gpio_pm[COMM_3] = 0; + config->gpio_pm[COMM_4] = 0; + config->gpio_pm[COMM_5] = 0; + variant_update_soc_chip_config(config); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63505 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac5f13f65fd1cf6281e1d05fef1219236ba2c51 Gerrit-Change-Number: 63505 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/romstage: Add desktop UserBd options
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63504 ) Change subject: soc/intel/alderlake/romstage: Add desktop UserBd options ...................................................................... soc/intel/alderlake/romstage: Add desktop UserBd options Add the desktop board types as per DOC #573387. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4 --- M src/soc/intel/alderlake/include/soc/romstage.h 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/63504/1 diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index 6504d32..3a22d25 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -12,7 +12,10 @@ /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, - BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_DESKTOP_1DPC = 1, + BOARD_TYPE_DESKTOP_2DPC = 2, + BOARD_TYPE_DESKTOP_2DPC_T_TOP_ASYM = 3, + BOARD_TYPE_DESKTOP_2DPC_T_TOP = 4, BOARD_TYPE_ULT_ULX = 5, BOARD_TYPE_ULT_ULX_T4 = 6, BOARD_TYPE_SERVER = 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/63504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4 Gerrit-Change-Number: 63504 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/msi/ms7d25: Add correct memory init configuration
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/63503 ) Change subject: mb/msi/ms7d25: Add correct memory init configuration ...................................................................... mb/msi/ms7d25: Add correct memory init configuration Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs. TEST=Include the microcode from vendor firmware and FSP blob from Intel R&DC. Boot the platform and see it executing ramstage. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/romstage_fsp_params.c 2 files changed, 18 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63503/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb Gerrit-Change-Number: 63503 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Select FSP2.3 for ADL-S
by Tim Wawrzynczak (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63456 ) Change subject: soc/intel/alderlake: Select FSP2.3 for ADL-S ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Patchset: PS2: > Secondly, the FSP for ADL-S IOT which is already public indicates v2.3 compliance in the header: […] Ack PS2: > Tim, I have selected DISPLAY_FSP_HEADER and it clearly shows FSP v2.3: […] Interesting, thanks, clearly that's the case, just unexpected to me that ADL-P and ADL-S are so divergent here. -- To view, visit https://review.coreboot.org/c/coreboot/+/63456 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7faa603cb19b530513f531a28bd8b283baba2 Gerrit-Change-Number: 63456 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 16:09:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/retimer.c: Do not access TCSS devices on ADL-S
by Tim Wawrzynczak (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Żygowski. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63501 ) Change subject: soc/intel/alderlake/retimer.c: Do not access TCSS devices on ADL-S ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Why not just modify the Makefile, e.g. ``` + +ifneq ($(SOC_INTEL_ALDERLAKE_PCH_S,y) ramstage-y += retimer.c +endif ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += tcss.c ``` It's likely that ADL-S boards would not include the DRIVERS_INTEL_USB4_RETIMER Kconfig option, so this retimer function is not needed in that case anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/63501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I562b7195371f87154698690362bf957881160b89 Gerrit-Change-Number: 63501 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 16:07:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: add GPIO configuration
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Michał Kopeć. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63490 ) Change subject: mb/msi/ms7d25: add GPIO configuration ...................................................................... Patch Set 8: (1 comment) File src/mainboard/msi/ms7d25/include/gpio.h: https://review.coreboot.org/c/coreboot/+/63490/comment/6851a10d_4a12fbcd PS8, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ Put the file directly into mainboard directory -- To view, visit https://review.coreboot.org/c/coreboot/+/63490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214 Gerrit-Change-Number: 63490 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:43:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add support to control CSE firmware update
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Rizwan Qureshi, Arthur Heymans, Patrick Rudolph, Sridhar Siricilla. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62715 ) Change subject: soc/intel/common: Add support to control CSE firmware update ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/62715/comment/de396a59_e8d390b8 PS3, Line 1067: * cse firmware update is skipped if SOC_INTEL_CSE_RW_UPDATE is not defined and : * runtime debug control flag is not enabled. > Ack ping for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/62715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba Gerrit-Change-Number: 62715 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:36:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022