Attention is currently required from: Robert Zieba, Bao Zheng, Marshall Dawson, Felix Held.
Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62795 )
Change subject: util: Add amdfwread utility
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Bao/Felix can you or someone else at AMD please review?
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Change subject: sc7280/qtiseclib blob update
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I got little confused on seeing deltas […]
Ok, it seems like there are many qtiseclib updates now that are outstanding. Can you just upload the current one and abandon all the others so we know what's the latest release?
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Attention is currently required from: Michał Żygowski.
Michał Żygowski has uploaded a new patch set (#5) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/63499 )
Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree
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mb/msi/ms7d25: add basic FSP configuration in devicetree
Configure some basic FSP parameters in devicetree for
to allow for booting an OS.
Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/mainboard/msi/ms7d25/devicetree.cb
1 file changed, 67 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63499/5
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Hello build bot (Jenkins), Igor Bagnucki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63463
to look at the new patch set (#6).
Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
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mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up
up to romstage where it returns from FSP memory init with an error.
What works:
- open-source CAR setup
- NCT6687D serial port with TX pin exposed on JBD1 header
- SMBus reading SPD from all 4 DIMMs
This board will serve as a reference board for enabling Alder Lake-S
support in coreboot. More code and functionalities will be added in
subsequent patches as src/soc/alderlake code will be improved for
PCH-S.
TEST=Extract the microcode from vendor firmware and include it in the
build. The platform should print the console on the serial port even
without FSP blob.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8
Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com>
---
A configs/config.msi_ms7d25
A src/mainboard/msi/ms7d25/Kconfig
A src/mainboard/msi/ms7d25/Kconfig.name
A src/mainboard/msi/ms7d25/Makefile.inc
A src/mainboard/msi/ms7d25/board_info.txt
A src/mainboard/msi/ms7d25/bootblock.c
A src/mainboard/msi/ms7d25/devicetree.cb
A src/mainboard/msi/ms7d25/dsdt.asl
A src/mainboard/msi/ms7d25/hda_verb.c
A src/mainboard/msi/ms7d25/mainboard.c
A src/mainboard/msi/ms7d25/romstage_fsp_params.c
11 files changed, 283 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/6
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