coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Selma Bensaid (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Jakub Czapiga, Tim Wawrzynczak, Julius Werner, Balaji Manigandan. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63240/comment/6cf84212_664ce447 PS3, Line 9: #3461454 > After looking at how external payloads are build in coreboot I came to conclusion, that enabling LIB […] Tim, I update the commit. Hope this what you meant. Jakub, sorry for the late answer. I wanted to avoid having coreboot/payloads/libpayload/configs/config.<BOARD> for all our boards, to reduce the maintenance effort. -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:35:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Selma Bensaid (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Balaji Manigandan. Hello Zhixing Ma, Bora Guvendik, Anil Kumar K, build bot (Jenkins), Jakub Czapiga, Tim Wawrzynczak, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63240 to look at the new patch set (#5). Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... libpayload/defconfig: enable vboot Lib Build After depthcharge patch https://crrev.com/c/3461454 merge, vboot needs to be built by libpayload. BUG=chrome-os-partner:226438207 TEST=Compiled brya and redrix in standalone mode. Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 --- M payloads/libpayload/configs/defconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63240/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Selma Bensaid (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Julius Werner, Balaji Manigandan. Hello Zhixing Ma, Bora Guvendik, Anil Kumar K, build bot (Jenkins), Jakub Czapiga, Tim Wawrzynczak, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63240 to look at the new patch set (#4). Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... libpayload/defconfig: enable vboot Lib Build After depthcharge patch #3461454 merge, vboot build need to be built by libpayload. BUG=b:226438207 TEST=Compiled brya and redrix in standalone mode. Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 --- M payloads/libpayload/configs/defconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63240/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 4 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Sridhar Siricilla (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 7: (2 comments) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/63293/comment/5b532eed_277b2aed PS7, Line 578: * Add Workaround to disable PCH USB2 Phy power gating as per Intel TA# 723158 to : * prevent possible display flicker issue. : * Enable or Disable PCH USB2 Phy power gating. : * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. > unrelated to the TA ? I said in general that usb2_phy_sus_pg_enable UPD can be disabled different purpose like debugging. As we all know there will be power impact if the UPD is not enabled. For now, we are disabling the UPD due to the TA. https://review.coreboot.org/c/coreboot/+/63293/comment/62d3cfbe_02feb4f3 PS7, Line 582: * > nit; extra blank line Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:23:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/msi/ms7d25: Add correct memory init configuration
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63503 ) Change subject: mb/msi/ms7d25: Add correct memory init configuration ...................................................................... mb/msi/ms7d25: Add correct memory init configuration Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs. TEST=Include the microcode from vendor firmware and FSP blob from Intel R&DC. Boot the platform and see it executing ramstage. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/romstage_fsp_params.c 2 files changed, 18 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63503/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index faf8c38..b5be153 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -6,6 +6,9 @@ # Sagv Configuration register "sagv" = "SaGv_Enabled" + register "RMT" = "0" + + register "enable_c6dram" = "1" # USB Configuration # TODO: Verify diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 412e3ab..389e359 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -9,22 +9,28 @@ static const struct mb_cfg ddr4_mem_config = { .type = MEM_TYPE_DDR4, + /* According to DOC #573387 rcomp no longer have to be provided */ .rcomp = { - /* Baseboard uses only 100ohm Rcomp resistor FIXME */ - .resistor = 100, + /* Baseboard uses only 100ohm Rcomp resistor */ + .resistor = 0, - /* Baseboard Rcomp target values FIXME */ - .targets = { 50, 20, 25, 25, 25 }, + /* Baseboard Rcomp target values */ + .targets = { 0 }, }, + /* DDR DIMM configuration does not need to set DQ/DQS maps */ + .dq_map = { 0 }, + .dqs_map = { 0 }, .ect = true, /* Early Command Training */ - .UserBd = BOARD_TYPE_DESKTOP, /* FIXME */ + .UserBd = BOARD_TYPE_DESKTOP, - .LpDdrDqDqsReTraining = 1, + .LpDdrDqDqsReTraining = 0, /* LPDDR only, set to 0 */ + + .CmdMirror = 0x33, .ddr_config = { - .dq_pins_interleaved = false, /* FIXME */ + .dq_pins_interleaved = true, }, }; @@ -44,5 +50,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + memupd->FspmConfig.FirstDimmBitMask = 0xA; + memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb Gerrit-Change-Number: 63503 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/Kconfig: Unselect IPU for ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63502 ) Change subject: soc/intel/alderlake/Kconfig: Unselect IPU for ADL-S ...................................................................... soc/intel/alderlake/Kconfig: Unselect IPU for ADL-S Alder Lake S CPUs do not have IPU device. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63502/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index a468e5d..b55788f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -89,7 +89,7 @@ select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT - select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IPU if !SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79b084273f407119d903ed6f0cadf0084e8dda6a Gerrit-Change-Number: 63502 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake/retimer.c: Do not access TCSS devices on ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63501 ) Change subject: soc/intel/alderlake/retimer.c: Do not access TCSS devices on ADL-S ...................................................................... soc/intel/alderlake/retimer.c: Do not access TCSS devices on ADL-S ADL-S does not have TCSS devices. Cut out the code for ADL-S. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I562b7195371f87154698690362bf957881160b89 --- M src/soc/intel/alderlake/retimer.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/63501/1 diff --git a/src/soc/intel/alderlake/retimer.c b/src/soc/intel/alderlake/retimer.c index 3fd9c2d..561994e 100644 --- a/src/soc/intel/alderlake/retimer.c +++ b/src/soc/intel/alderlake/retimer.c @@ -7,6 +7,7 @@ int retimer_get_index_for_typec(uint8_t typec_port) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) int ec_port = 0; const struct device *tcss_port_arr[] = { @@ -26,7 +27,7 @@ if (is_dev_enabled(tcss_port_arr[i])) ec_port++; } - +#endif // Code should not come here if typec_port input is correct return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I562b7195371f87154698690362bf957881160b89 Gerrit-Change-Number: 63501 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
by Michał Żygowski (Code Review) 08 Apr '22

08 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63500 ) Change subject: soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S ...................................................................... soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/63500/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 2eeae42..9162cd9 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -98,11 +98,11 @@ select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_COMMON_BLOCK_TCSS if !SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC - select SOC_INTEL_COMMON_BLOCK_USB4 - select SOC_INTEL_COMMON_BLOCK_USB4_PCIE - select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_USB4 if !SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_COMMON_BLOCK_USB4_PCIE if !SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_COMMON_BLOCK_USB4_XHCI if !SOC_INTEL_ALDERLAKE_PCH_S select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BASECODE diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 825cfd5..e3564aa 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -37,7 +37,7 @@ ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c -ramstage-y += retimer.c +ramstage-$(CONFIG_DRIVERS_INTEL_USB4_RETIMER) += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += tcss.c -- To view, visit https://review.coreboot.org/c/coreboot/+/63500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Gerrit-Change-Number: 63500 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Add a common romstage entry
by Raul Rangel (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Angel Pons, Arthur Heymans, Fred Reitberger, Patrick Rudolph, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55067 ) Change subject: arch/x86: Add a common romstage entry ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Gerrit-Change-Number: 55067 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:14:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/{brya, brask}: Disable PCH USB2 phy power gating
by Tim Wawrzynczak (Code Review) 08 Apr '22

08 Apr '22

Attention is currently required from: Paul Menzel, Sridhar Siricilla, Angel Pons. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/{brya, brask}: Disable PCH USB2 phy power gating ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 08 Apr 2022 15:05:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022