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Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63411 )
Change subject: mb/prodrive/atlas: Update GPIOs
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/prodrive/atlas/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/63411/comment/d7bc72f5_92c76e76
PS1, Line 14: EC_IN_RW
> Ah, looks like the `EC_SMI_N` signal on ADLRVP has been repurposed as `EC_IN_RW` for ChromeOS usecas […]
Done
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Change subject: util/intelp2m: Add support for Alder Lake macro generation
......................................................................
Patch Set 5:
(2 comments)
File util/intelp2m/platforms/adl/macro.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/e6cbb49a_1dacaedc
PS3, Line 99: macro := common.GetInstanceMacro(PlatformSpecific{InheritanceMacro : cnl.PlatformSpecific{}},
: fields.InterfaceGet())
> Applied, still same issue though: […]
Done
File util/intelp2m/platforms/adl/macro.go:
https://review.coreboot.org/c/coreboot/+/63403/comment/91052df9_42985b71
PS4, Line 52: var remapping = map[uint8]uint32{
> According to doc #621483, this is correct, and CB:63467 is wrong. […]
Done
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Change subject: mb/prodrive/atlas: Update GPIOs
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/prodrive/atlas/early_gpio.c:
https://review.coreboot.org/c/coreboot/+/63411/comment/4c1c4a17_60d7b125
PS1, Line 14: EC_IN_RW
> yes correct it is EC_SMI_N, which is the same as RVP. […]
Ah, looks like the `EC_SMI_N` signal on ADLRVP has been repurposed as `EC_IN_RW` for ChromeOS usecase. Given that Atlas doesn't use ChromeOS, I'd use the `EC_SMI_N` name from the schematics.
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Hello Michał Żygowski,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: mb/msi/ms7d25: add basic FSP configuration in devicetree
......................................................................
mb/msi/ms7d25: add basic FSP configuration in devicetree
Configure some basic FSP parameters in devicetree for
to allow for booting an OS.
Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/mainboard/msi/ms7d25/devicetree.cb
1 file changed, 66 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63499/3
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Hello build bot (Jenkins), Michał Żygowski, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/intel/alderlake: add GPIO definitions for PCH-S
......................................................................
soc/intel/alderlake: add GPIO definitions for PCH-S
Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles
the split.
Based on:
- Intel PCH-S EDS Vol2 (#621483)
- Alderlake-S FSP
- slimbootloader sources
- Linux alderlake-pinctrl driver
Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/soc/intel/alderlake/Makefile.inc
M src/soc/intel/alderlake/acpi/gpio.asl
M src/soc/intel/alderlake/fsp_params.c
A src/soc/intel/alderlake/gpio_pch_s.c
M src/soc/intel/alderlake/include/soc/gpio.h
A src/soc/intel/alderlake/include/soc/gpio_defs_pch_s.h
A src/soc/intel/alderlake/include/soc/gpio_soc_defs_pch_s.h
M src/soc/intel/alderlake/include/soc/pmc.h
M src/soc/intel/alderlake/romstage/fsp_params.c
9 files changed, 1,159 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63467/7
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Hello Michał Żygowski, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S
......................................................................
soc/intel/alderlake: add chipset devicetree for ADL-S
Add chipset devicetree and power limits for AlderLake-S platform.
Based on Intel docs #619501 and #619362.
Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
A src/soc/intel/alderlake/chipset_pch_s.cb
M src/soc/intel/alderlake/fsp_params.c
4 files changed, 213 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63493/3
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Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
Patch Set 8:
(6 comments)
File util/inteltool/gpio_names/alderlake_h.h:
https://review.coreboot.org/c/coreboot/+/63374/comment/c655fb3e_cc58a901
PS8, Line 102: const char *const alderlake_pch_h_group_d_names[] = {
> The DOC #618659 has copy-pasta error, the NF6 column should obviously contain: […]
Done
File util/inteltool/inteltool.h:
https://review.coreboot.org/c/coreboot/+/63374/comment/a6c63acf_1f658ebb
PS8, Line 356: #define PCI_DEVICE_ID_INTEL_CORE_ADL_ID_H_6_8 0x4641 /* Alderlake H 6+8 */
> This is H processor line, different from S and HX line which the dump/patch is for.
Removed
https://review.coreboot.org/c/coreboot/+/63374/comment/20455535_0a97ecbd
PS8, Line 436: #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
> There are more IDs based on the stepping for S LGA and HX SBGA
Added remaining device IDs for ADL-S
https://review.coreboot.org/c/coreboot/+/63374/comment/43b47e20_43a4d027
PS8, Line 437: #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0
: #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
> Not an ADL-S/HX GT devices
Removed
File util/inteltool/inteltool.c:
https://review.coreboot.org/c/coreboot/+/63374/comment/dae05307_4cebb5fa
PS8, Line 173: { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_ADL_ID_H_6_8,
: "12th generation (Alder Lake H family) Core Processor (Mobile)" },
> Not an ADL-S/HX line
Removed
https://review.coreboot.org/c/coreboot/+/63374/comment/2910fd96_6a7aeabc
PS8, Line 545: { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_P_GT2,
: "Intel(R) AlderLake-P GT2" },
: { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ADL_M_GT1,
: "Intel(R) AlderLake-M GT1" },
> Not an ADL-S/HX GT devices
Removed
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Hello Felix Singer, build bot (Jenkins), Michał Żygowski, Paul Menzel, Stefan Reinauer, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
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Change subject: util/inteltool: Add support for Alder Lake chips detection and GPIOs
......................................................................
util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.
PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362).
TEST=dump GPIOs on i5-12600K with Z690 chipset
Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com>
---
M util/inteltool/gpio.c
M util/inteltool/gpio_groups.c
A util/inteltool/gpio_names/alderlake_h.h
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/pcr.c
6 files changed, 610 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63374/9
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Igor Bagnucki has uploaded a new patch set (#5) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/63463 )
Change subject: mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
......................................................................
mainboard/msi/ms7d25: Add early support for MSI PRO Z690-A DDR4 WIFI
Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up
up to romstage where it returns from FSP memory init with an error.
What works:
- open-source CAR setup
- NCT6687D serial port with TX pin exposed on JBD1 header
- SMBus reading SPD from all 4 DIMMs
This board will serve as a reference board for enabling Alder Lake-S
support in coreboot. More code and functionalities will be added in
subsequent patches as src/soc/alderlake code will be improved for
PCH-S.
TEST=Extract the microcode from vendor firmware and include it in the
build. The platform should print the console on the serial port even
without FSP blob.
Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8
Signed-off-by: Igor Bagnucki <igor.bagnucki(a)3mdeb.com>
---
A configs/config.msi_ms7d25
A src/mainboard/msi/ms7d25/Kconfig
A src/mainboard/msi/ms7d25/Kconfig.name
A src/mainboard/msi/ms7d25/Makefile.inc
A src/mainboard/msi/ms7d25/board_info.txt
A src/mainboard/msi/ms7d25/bootblock.c
A src/mainboard/msi/ms7d25/devicetree.cb
A src/mainboard/msi/ms7d25/dsdt.asl
A src/mainboard/msi/ms7d25/hda_verbs.c
A src/mainboard/msi/ms7d25/mainboard.c
A src/mainboard/msi/ms7d25/romstage_fsp_params.c
11 files changed, 284 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/63463/5
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Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63495 )
Change subject: mb/google/brya/var/brya0: Change MAX98360 AMP interface to I2S1
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> please add signed-off
Done
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