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Change subject: soc/intel/alderlake: Add support to update the FIVR configs
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File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63497/comment/a67a9dc7_4cdb837d
PS1, Line 85: BIT4
Copy-paste error? S0 is bit 5
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Change subject: cpu/x86/smm_module_loader: Add a convenient ss_top
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Change subject: cpu/x86/smm: Drop 'entry' struct element
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Change subject: cpu/x86/mp_init.c: Drop 'real' vs 'used' save state
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Change subject: cpu/x86/smm_module_loader: Drop superfluous check
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Change subject: cpu/qemu-x86: Allow up to 255 cores
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