coreboot-gerrit April 2022

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Taniya Das, Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 10: (3 comments) File src/soc/qualcomm/common/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/b4e2b63c_c21fa28d PS8, Line 103: if (hz != clk_cfg[idx].hz) > Please make sure you fix the num_perfs=0 in sc7180 as well. Done File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/0f2c08f2_4386c96c PS7, Line 412: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > There are three more tabs in front of this line than there should be (or is there something wrong ab […] That actually shouldn't be there at all. THanks. File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/9860a8f3_75776ea1 PS8, Line 418: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > Yes that works too. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 10 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 00:44:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Shelley Chen, Taniya Das, Paul Menzel. Hello build bot (Jenkins), Taniya Das, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63289 to look at the new patch set (#10). Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... soc/qualcomm/common: Make clock_configure() check for exact matches Previously, clock_configure() will configure the clocks to round up to the next highest frequency bin. This seems non-intuitive. Changing the logic to find an exact frequency match and will halt booting if not found. Recently fixed a bug in CB:63311, where the clock was being set incorrectly for emmc and was able to find it because of this stricter check. BUG=b:198627043 BRANCH=None TEST=build herobrine image and try to set SPI frequency to number not supported. Ensure device doesn't boot. Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/clock.c M src/soc/qualcomm/common/include/soc/clock_common.h M src/soc/qualcomm/sc7180/clock.c M src/soc/qualcomm/sc7280/clock.c 4 files changed, 35 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63289/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 10 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google,samsung: Drop init_bootmode_straps()
by Julius Werner (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Angel Pons, Kyösti Mälkki, Patrick Rudolph. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59008 ) Change subject: mb/google,samsung: Drop init_bootmode_straps() ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/beltino/chromeos.c: https://review.coreboot.org/c/coreboot/+/59008/comment/64b86745_2f135080 PS3, Line 16: !get_recovery_mode_switch(), "presence"}, > Well get_recovery_mode_switch() is sampled src/security/vboot/vboot_logic. […] Oh, sorry, I didn't read closely enough, I though this said "recovery". "presence" is actually a different thing, and that one is resampled at runtime and still used by depthcharge today. So there, having the GPIO_REC_MODE in here is actually important. On Chromeboxes like Beltino, the recovery button has two separate functions -- one is that when you hold it down during boot it enters recovery mode, and another is that for certain security-critical decisions (like enabling developer mode) we require the user to press it as a physical presence signal to prove user intent (because we don't trust the USB keyboard not to get hacked). On some platforms, we use a different button (e.g. power) for this presence signal. That's why "recovery", "power" and "presence" are all logically separate things in lb_gpio, although often the same physical GPIO may implement more than one of these logical functions. Not all boards have a "presence" in their tables, only those without trusted built-in keyboards. That's why you may not have seen it on most newer boards. Also I think we took a different route to approach the same problem on some of the newer Chromeboxes, but the ones that have a "presence" should definitely keep it. -- To view, visit https://review.coreboot.org/c/coreboot/+/59008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Gerrit-Change-Number: 59008 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 00:40:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Julius Werner (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Shelley Chen, Taniya Das, Paul Menzel. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 9: (3 comments) File src/soc/qualcomm/common/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/3b1a2c12_acb4566a PS8, Line 103: if (hz != clk_cfg[idx].hz) > Done Please make sure you fix the num_perfs=0 in sc7180 as well. File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/e5fd5331_81561286 PS7, Line 412: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > I'm not sure what you're referring to? Can you be more specific? There are three more tabs in front of this line than there should be (or is there something wrong about how Gerrit displays it?). File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/27f56644_6644125a PS8, Line 418: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > Ok, I see. We were still passing in hz to clock_configure(). How about we pass in mdss_clk_cfg. […] Yes that works too. -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 00:13:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tpm: Refactor TPM Kconfig dimensions
by Julius Werner (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Stefan Ott, Felix Singer, Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Jes Klinke, Nico Huber, Sean Rhodes, Michał Żygowski, Johnny Lin, Christian Walter, Werner Zeh, Alexander Couzens, Yu-Ping Wu, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Angel Pons, Michael Niewöhner, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63424 ) Change subject: tpm: Refactor TPM Kconfig dimensions ...................................................................... Patch Set 13: (4 comments) File src/drivers/crb/chip.c: https://review.coreboot.org/c/coreboot/+/63424/comment/8d2a09ef_a4c7fdaa PS13, Line 17: .acpi_fill_ssdt = crb_tpm_fill_ssdt, The definitions of these two functions need to move into this file too, otherwise you have missing reference errors here when building without CONFIG_TPM. File src/drivers/pc80/tpm/chip.c: https://review.coreboot.org/c/coreboot/+/63424/comment/cc8c16b8_57c61344 PS13, Line 14: u8 value = read8(TIS_REG(locality, TIS_REG_INT_VECTOR)); Jenkins complains that you don't have TIS_REG() in this context. Another good reason to move most of this back to tis.c. https://review.coreboot.org/c/coreboot/+/63424/comment/e6d7a927_34546d52 PS13, Line 194: if (CONFIG(TPM)) Well, in this case moving lpc_tpm_ops and everything below it into this file isn't really necessary because there's this CONFIG(TPM) check here that kills it all for the NO_TPM case anyway. In particular, some of that calls code from tis.c (like tis_open()) which then wouldn't work. The way you did it now isn't broken, but I think it would make more sense to keep the other stuff in tis.c. (Why this behaves differently than the CRB and I2C drivers for the NO_TPM case and doesn't register the tpm_ops with the ACPI SSDT stuff, I do not know. Most likely one of those behaviors is correct for all of them and at least one of these drivers is buggy, but I don't know which is which. Maybe some of the x86 folks on this patch can give more insight on how this should change. If we want to write an SSDT entry for NO_TPM and it needs to do actual TPM accesses to fill out those values, that would be a problem.) File src/mainboard/google/volteer/mainboard.c: https://review.coreboot.org/c/coreboot/+/63424/comment/01533c67_5469834b PS10, Line 87: CONFIG(TPM_GOOGLE_CR50) > Good catch again. Actually, with the new _CR50/_TI50 split, the SPI_TPM part could be dropped here. […] According to the comment here, it sounds like the SPI_TPM is important ("Negotiation of long interrupt pulses is only supported via SPI."). I guess maybe I2C doesn't work at all on those platforms, so it could go either way... but anyway, sounds like this code isn't "wrong". edit: Oh right, and I didn't de-Morgan correctly when I suggested this. Thanks for paying attention! -- To view, visit https://review.coreboot.org/c/coreboot/+/63424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Gerrit-Change-Number: 63424 Gerrit-PatchSet: 13 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Ott <coreboot(a)desire.ch> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jes Klinke <jbk(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 00:08:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jes Klinke <jbk(a)chromium.org> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina: Maintain a single copy of PSP Level2 entries
by Karthik Ramasubramanian (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63510 ) Change subject: soc/amd/sabrina: Maintain a single copy of PSP Level2 entries ...................................................................... soc/amd/sabrina: Maintain a single copy of PSP Level2 entries If verified boot uses 2 RW FW slots, configure amdfwtool to maintain single copy of PSP Level2 entries. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I94eea693139b714c321b4be89380342ec7a21222 --- M src/soc/amd/sabrina/Makefile.inc 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63510/1 diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index b7b538e..fdad9b7 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -189,6 +189,9 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) +# If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant +OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) + # Add all the files listed in the config file POUND_SIGN=$(call strip_quotes, "\#") DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /*/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) @@ -212,7 +215,8 @@ $(OPT_EFS_SPI_MICRON_FLAG) \ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --soc-name "Sabrina" \ - --flashsize $(CONFIG_ROM_SIZE) + --flashsize $(CONFIG_ROM_SIZE) \ + $(OPT_RECOVERY_AB_SINGLE_COPY) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/63510 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94eea693139b714c321b4be89380342ec7a21222 Gerrit-Change-Number: 63510 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/amdfwtool: Maintain one copy of PSP Level2 entries
by Karthik Ramasubramanian (Code Review) 09 Apr '22

09 Apr '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63509 ) Change subject: util/amdfwtool: Maintain one copy of PSP Level2 entries ...................................................................... util/amdfwtool: Maintain one copy of PSP Level2 entries AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/63509/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 23273e6..878de33 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -857,6 +857,10 @@ if (pspdir2_b != NULL) integrate_psp_ab(ctx, pspdir, pspdir2_b, ish_b_dir, AMD_FW_RECOVERYAB_B, soc_id); + else + integrate_psp_ab(ctx, pspdir, pspdir2, ish_b_dir, + AMD_FW_RECOVERYAB_B, soc_id); + count = pspdir->header.num_entries; } else if (pspdir2 != NULL) { assert_fw_entry(count, MAX_PSP_ENTRIES, ctx); @@ -1202,6 +1206,7 @@ AMDFW_OPT_GEC, AMDFW_OPT_COMBO, AMDFW_OPT_RECOVERY_AB, + AMDFW_OPT_RECOVERY_AB_SINGLE_COPY, AMDFW_OPT_MULTILEVEL, AMDFW_OPT_NVRAM, @@ -1250,6 +1255,7 @@ /* PSP Directory Table items */ {"combo-capable", no_argument, 0, AMDFW_OPT_COMBO }, {"recovery-ab", no_argument, 0, AMDFW_OPT_RECOVERY_AB }, + {"recovery-ab-single-copy", no_argument, 0, AMDFW_OPT_RECOVERY_AB_SINGLE_COPY }, {"multilevel", no_argument, 0, AMDFW_OPT_MULTILEVEL }, {"nvram", required_argument, 0, AMDFW_OPT_NVRAM }, {"soft-fuse", required_argument, 0, AMDFW_OPT_FUSE }, @@ -1538,6 +1544,10 @@ case AMDFW_OPT_RECOVERY_AB: cb_config.recovery_ab = true; break; + case AMDFW_OPT_RECOVERY_AB_SINGLE_COPY: + cb_config.recovery_ab = true; + cb_config.recovery_ab_single_copy = true; + break; case AMDFW_OPT_MULTILEVEL: cb_config.multi_level = true; break; @@ -1840,7 +1850,7 @@ pspdir2 = new_psp_dir(&ctx, cb_config.multi_level); integrate_psp_firmwares(&ctx, pspdir2, NULL, NULL, amd_psp_fw_table, PSPL2_COOKIE, soc_id, &cb_config); - if (cb_config.recovery_ab) { + if (cb_config.recovery_ab && !cb_config.recovery_ab_single_copy) { /* B is same as above directories for A */ /* Skip creating pspdir2_b here to save flash space. Related * biosdir2_b will be skipped automatically. */ diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 3af4e94..4af2dac 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -278,6 +278,7 @@ bool s0i3; bool have_mb_spl; bool recovery_ab; + bool recovery_ab_single_copy; bool need_ish; } amd_cb_config; -- To view, visit https://review.coreboot.org/c/coreboot/+/63509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Gerrit-Change-Number: 63509 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tpm: Refactor TPM Kconfig dimensions
by Jes Klinke (Code Review) 09 Apr '22

09 Apr '22

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Change in coreboot[master]: tpm: Refactor TPM Kconfig dimensions
by Jes Klinke (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Stefan Ott, Felix Singer, Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Nico Huber, Sean Rhodes, Michał Żygowski, Johnny Lin, Christian Walter, Werner Zeh, Alexander Couzens, Yu-Ping Wu, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Angel Pons, Michael Niewöhner, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak. Hello Felix Singer, Stefan Ott, build bot (Jenkins), Patrick Rudolph, Jonathan Zhang, Nick Vaccaro, Arthur Heymans, Andrey Petrov, Piotr Król, Sean Rhodes, Nico Huber, Michał Żygowski, Johnny Lin, Christian Walter, siemens-bot, Werner Zeh, Alexander Couzens, Yu-Ping Wu, Tim Chu, Frans Hendriks, Tristan Corrick, Jeremy Soller, Angel Pons, Julius Werner, Michael Niewöhner, Erik van den Bogaert, Tim Crawford, Maxim Polyakov, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63424 to look at the new patch set (#13). Change subject: tpm: Refactor TPM Kconfig dimensions ...................................................................... tpm: Refactor TPM Kconfig dimensions Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of the above is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk(a)chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e --- M Documentation/getting_started/kconfig.md M src/drivers/crb/Kconfig M src/drivers/crb/Makefile.inc A src/drivers/crb/chip.c M src/drivers/crb/tis.c M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/Makefile.inc M src/drivers/pc80/tpm/Kconfig M src/drivers/pc80/tpm/Makefile.inc A src/drivers/pc80/tpm/chip.c M src/drivers/pc80/tpm/tis.c M src/drivers/spi/tpm/Kconfig M src/drivers/spi/tpm/Makefile.inc M src/drivers/spi/tpm/tpm.c M src/drivers/tpm/Makefile.inc M src/mainboard/acer/aspire_vn7_572g/Kconfig M src/mainboard/asrock/b85m_pro4/Kconfig M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/h61-series/Kconfig.name M src/mainboard/asus/p8x7x-series/Kconfig.name M src/mainboard/clevo/cml-u/Kconfig M src/mainboard/clevo/kbl-u/Kconfig M src/mainboard/clevo/tgl-u/Kconfig M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/facebook/fbg1701/Kconfig M src/mainboard/facebook/monolith/Kconfig M src/mainboard/foxconn/g41s-k/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/google/asurada/Kconfig M src/mainboard/google/auron/Kconfig M src/mainboard/google/beltino/Kconfig M src/mainboard/google/brya/Kconfig M src/mainboard/google/butterfly/Kconfig M src/mainboard/google/cherry/Kconfig M src/mainboard/google/corsola/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/daisy/Kconfig M src/mainboard/google/dedede/Kconfig M src/mainboard/google/deltaur/Kconfig M src/mainboard/google/drallion/Kconfig M src/mainboard/google/eve/Kconfig M src/mainboard/google/fizz/Kconfig M src/mainboard/google/foster/Kconfig M src/mainboard/google/gale/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/google/gru/Kconfig M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/hatch/Kconfig M src/mainboard/google/herobrine/Kconfig M src/mainboard/google/herobrine/bootblock.c M src/mainboard/google/jecht/Kconfig M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kukui/Kconfig M src/mainboard/google/link/Kconfig M src/mainboard/google/nyan_big/Kconfig M src/mainboard/google/nyan_blaze/Kconfig M src/mainboard/google/oak/Kconfig M src/mainboard/google/octopus/Kconfig M src/mainboard/google/parrot/Kconfig M src/mainboard/google/peach_pit/Kconfig M src/mainboard/google/poppy/Kconfig M src/mainboard/google/rambi/Kconfig M src/mainboard/google/reef/Kconfig M src/mainboard/google/sarien/Kconfig M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/slippy/Kconfig M src/mainboard/google/smaug/Kconfig M src/mainboard/google/storm/Kconfig M src/mainboard/google/stout/Kconfig M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/veyron/Kconfig M src/mainboard/google/veyron_mickey/Kconfig M src/mainboard/google/veyron_rialto/Kconfig M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/chronicler/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/variant.c M src/mainboard/google/zork/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/folio_9480m/Kconfig M src/mainboard/hp/snb_ivb_laptops/Kconfig M src/mainboard/hp/z220_series/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/baskingridge/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/galileo/Kconfig M src/mainboard/intel/glkrvp/Kconfig M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/shadowmountain/Kconfig M src/mainboard/intel/strago/Kconfig M src/mainboard/intel/tglrvp/Kconfig M src/mainboard/intel/wtm2/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/kontron/mal10/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t440p/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/w541/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/libretrend/lt1000/Kconfig M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/opencellular/elgon/Kconfig M src/mainboard/pcengines/apu1/Kconfig M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/prodrive/hermes/Kconfig M src/mainboard/protectli/vault_kbl/Kconfig M src/mainboard/purism/librem_cnl/Kconfig.name M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/mainboard/siemens/chili/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig M src/mainboard/siemens/mc_apl1/variants/mc_apl6/Kconfig M src/mainboard/siemens/mc_ehl/Kconfig M src/mainboard/starlabs/labtop/Kconfig M src/mainboard/starlabs/lite/Kconfig M src/mainboard/supermicro/x11-lga1151-series/Kconfig M src/mainboard/supermicro/x9sae/Kconfig M src/mainboard/system76/addw1/Kconfig M src/mainboard/system76/bonw14/Kconfig M src/mainboard/system76/cml-u/Kconfig M src/mainboard/system76/darp7/Kconfig M src/mainboard/system76/galp5/Kconfig M src/mainboard/system76/gaze15/Kconfig M src/mainboard/system76/gaze16/Kconfig M src/mainboard/system76/kbl-u/Kconfig M src/mainboard/system76/lemp10/Kconfig M src/mainboard/system76/lemp9/Kconfig M src/mainboard/system76/oryp5/Kconfig M src/mainboard/system76/oryp6/Kconfig M src/mainboard/system76/oryp8/Kconfig M src/mainboard/system76/whl-u/Kconfig M src/mainboard/up/squared/Kconfig M src/security/tpm/Kconfig M src/security/tpm/Makefile.inc M src/security/tpm/tss/vendor/cr50/Kconfig M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_logic.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/Makefile.inc M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/tigerlake/Kconfig M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/Makefile.inc M src/vendorcode/google/chromeos/cse_board_reset.c 163 files changed, 496 insertions(+), 487 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/63424/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/63424 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Gerrit-Change-Number: 63424 Gerrit-PatchSet: 13 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski 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Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Taniya Das, Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 9: (4 comments) File src/soc/qualcomm/common/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/93bf5dbd_305a56ca PS8, Line 103: if (hz != clk_cfg[idx].hz) > Wait! Wait wait wait... sorry, should have seen this earlier. […] Done File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/9c3f5f26_ceceb1dc PS7, Line 412: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > This isn't enough: for the (clk_type != MDSS_CLK_MDP) clocks, we never get here. […] Done https://review.coreboot.org/c/coreboot/+/63289/comment/6d023640_0de87e26 PS7, Line 412: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > Indentation? I'm not sure what you're referring to? Can you be more specific? File src/soc/qualcomm/sc7280/clock.c: https://review.coreboot.org/c/coreboot/+/63289/comment/10fe1dac_06eb62d6 PS8, Line 418: mdss_clk_cfg.hz = mdss_mdp_cfg[idx].hz; > Well, now you're again risking that `mdss_clk_cfg.hz` and `hz` don't match, though. […] Ok, I see. We were still passing in hz to clock_configure(). How about we pass in mdss_clk_cfg.hz instead of modifying the parameter? -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 9 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Fri, 08 Apr 2022 23:37:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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