coreboot-gerrit April 2022

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Change in coreboot[master]: [RFC] ChromeOS: Declare CHROMEOS_NO_GPIOS
by Kyösti Mälkki (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Julius Werner, Fred Reitberger, Yu-Ping Wu, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner, Fred Reitberger, Yu-Ping Wu, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/58956 to look at the new patch set (#7). Change subject: [RFC] ChromeOS: Declare CHROMEOS_NO_GPIOS ...................................................................... [RFC] ChromeOS: Declare CHROMEOS_NO_GPIOS Implementation of fill_lb_gpios() is not about VBOOT but providing payload with information of bootmode. Change-Id: I9f1eaaeffe388a7f8a7fc2430b6593eb8298461b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/coreboot_table.c M src/mainboard/amd/chausie/Kconfig M src/mainboard/amd/chausie/chromeos.c M src/mainboard/amd/majolica/Kconfig M src/mainboard/amd/majolica/chromeos.c M src/mainboard/google/corsola/Kconfig M src/mainboard/google/mistral/Kconfig M src/mainboard/google/mistral/chromeos.c M src/security/vboot/bootmode.c M src/vendorcode/google/chromeos/Kconfig 10 files changed, 9 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/58956/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/58956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f1eaaeffe388a7f8a7fc2430b6593eb8298461b Gerrit-Change-Number: 58956 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google,samsung: Drop init_bootmode_straps()
by Kyösti Mälkki (Code Review) 09 Apr '22

09 Apr '22

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59008 ) Change subject: mb/google,samsung: Drop init_bootmode_straps() ...................................................................... mb/google,samsung: Drop init_bootmode_straps() Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59008 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/include/bootmode.h M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/jecht/chromeos.c D src/mainboard/google/jecht/romstage.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/early_init.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/intel/broadwell/pch/Makefile.inc 10 files changed, 9 insertions(+), 173 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 12c9f58..0871f8f 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -6,7 +6,6 @@ #include <stdbool.h> /* functions implemented per mainboard: */ -void init_bootmode_straps(void); int get_write_protect_state(void); int get_recovery_mode_switch(void); int get_recovery_mode_retrain_switch(void); diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 227e595..0e01895 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <bootmode.h> #include <boot/coreboot_tables.h> #include <device/device.h> @@ -10,9 +9,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -25,44 +21,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); } -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + return !get_gpio(GPIO_REC_MODE); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index d8ecb4e..563e32b 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -6,15 +6,10 @@ #include <device/device.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> -#include <ec/google/chromeec/ec.h> #include <soc/chromeos.h> -#include <soc/sata.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "onboard.h" -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -27,44 +22,14 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); } -static bool raw_recovery_mode_switch(void) -{ - return !get_gpio(GPIO_REC_MODE); -} - -int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - int get_recovery_mode_switch(void) { - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO12 = RECOVERY_L, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - /* Developer: Virtual */ - - pci_s_write_config32(dev, SATA_SP, flags); + return !get_gpio(GPIO_REC_MODE); } static const struct cros_gpio cros_gpios[] = { diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c deleted file mode 100644 index 5c978ba..0000000 --- a/src/mainboard/google/jecht/romstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootmode.h> -#include <console/console.h> -#include <ec/google/chromeec/ec.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/romstage.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8772f/it8772f.h> -#include "onboard.h" - -void mainboard_post_raminit(const int s3resume) -{ - if (CONFIG(CHROMEOS)) - init_bootmode_straps(); -} diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index ba5eabe..7761c69 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -4,16 +4,12 @@ #include <boot/coreboot_tables.h> #include <device/pci_ops.h> #include <device/device.h> -#include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - #include "ec.h" #include <ec/smsc/mec1308/ec.h> @@ -36,12 +32,12 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); } -static bool raw_recovery_mode_switch(void) +int get_recovery_mode_switch(void) { return !get_gpio(GPIO_REC_MODE); } @@ -58,33 +54,6 @@ return (gen_pmcon_1 >> 9) & 1; } -int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - pci_s_write_config32(dev, SATA_SP, flags); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 26c8826..fd0f944 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -182,11 +182,6 @@ read_spd(&spd[0], 0x50, id_only); } -void mainboard_early_init(int s3resume) -{ - init_bootmode_straps(); -} - int mainboard_should_reset_usb(int s3resume) { return !s3resume; diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c index 61782f8..739b577 100644 --- a/src/mainboard/samsung/stumpy/chromeos.c +++ b/src/mainboard/samsung/stumpy/chromeos.c @@ -10,9 +10,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "onboard.h" -#define FLAG_SPI_WP 0 -#define FLAG_REC_MODE 1 - void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { @@ -33,12 +30,12 @@ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } -static bool raw_write_protect_state(void) +int get_write_protect_state(void) { return get_gpio(GPIO_SPI_WP); } -static bool raw_recovery_mode_switch(void) +int get_recovery_mode_switch(void) { return !get_gpio(GPIO_REC_MODE); } @@ -50,34 +47,6 @@ return (gen_pmcon_1 >> 9) & 1; } -int get_write_protect_state(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; -} - -int get_recovery_mode_switch(void) -{ - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; -} - -void init_bootmode_straps(void) -{ - u32 flags = 0; - const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); - - /* Write Protect: GPIO68 = CHP3_SPI_WP, active high */ - if (raw_write_protect_state()) - flags |= (1 << FLAG_SPI_WP); - - /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (raw_recovery_mode_switch()) - flags |= (1 << FLAG_REC_MODE); - - pci_s_write_config32(dev, SATA_SP, flags); -} - static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index dfb1f4d0..97f656a 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -164,11 +164,6 @@ { 1, 0, 5 }, /* P13: Back port (OC5) */ }; -void mainboard_early_init(int s3resume) -{ - init_bootmode_straps(); -} - int mainboard_should_reset_usb(int s3resume) { if (s3resume) { diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index a6f626a..1b6e744 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -16,10 +16,6 @@ #include <southbridge/intel/common/pmclib.h> #include <elog.h> -__weak void mainboard_early_init(int s3_resume) -{ -} - __weak void mainboard_late_rcba_config(void) { } @@ -71,8 +67,6 @@ post_code(0x38); - mainboard_early_init(s3resume); - post_code(0x39); if (CONFIG(INTEL_TXT)) { diff --git a/src/soc/intel/broadwell/pch/Makefile.inc b/src/soc/intel/broadwell/pch/Makefile.inc index 1afa92b..5bd09ea 100644 --- a/src/soc/intel/broadwell/pch/Makefile.inc +++ b/src/soc/intel/broadwell/pch/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += finalize.c ramstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c +verstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c ramstage-y += hda.c ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/59008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Gerrit-Change-Number: 59008 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google,samsung: Drop init_bootmode_straps()
by Kyösti Mälkki (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Angel Pons, Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59008 ) Change subject: mb/google,samsung: Drop init_bootmode_straps() ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/beltino/chromeos.c: https://review.coreboot.org/c/coreboot/+/59008/comment/25b995ba_9743903e PS3, Line 16: !get_recovery_mode_switch(), "presence"}, > Oh, sorry, I didn't read closely enough, I though this said "recovery". […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/59008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcaf30c622bf5dc0f1295f2639c656086d01ff7e Gerrit-Change-Number: 59008 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 02:48:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... Patch Set 10: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63251/comment/e6e984ad_6c718840 PS9, Line 146: }; > Thanks! Can you please also add a […] I think it's a little bit overkill, and it will reduce the readability. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 02:12:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t
by Jianjun Wang (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Hung-Te Lin, Jakub Czapiga, Julius Werner, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63494 ) Change subject: coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t ...................................................................... Patch Set 2: (7 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/63494/comment/e0157482_645fa854 PS1, Line 141: uint64_t hwrpb; > This too please, while we're doing this. Done https://review.coreboot.org/c/coreboot/+/63494/comment/e299314b_4da55320 PS1, Line 209: uint64_t forward; > ditto Done https://review.coreboot.org/c/coreboot/+/63494/comment/e71f1b47_3fc34929 PS1, Line 267: uint64_t physical_address; > ditto Done https://review.coreboot.org/c/coreboot/+/63494/comment/3223b802_66a5bfb5 PS1, Line 305: uint64_t range_start; > and here Done https://review.coreboot.org/c/coreboot/+/63494/comment/f0911b16_3202a1d1 PS1, Line 315: uint64_t cbmem_addr; > and here Done https://review.coreboot.org/c/coreboot/+/63494/comment/46b5a177_f0a3e073 PS1, Line 354: uint64_t boot_media_size; > all of these Done https://review.coreboot.org/c/coreboot/+/63494/comment/8e842e2d_da09e378 PS1, Line 364: uint64_t address; > and this Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 2 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Sat, 09 Apr 2022 02:04:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Jianjun Wang. Hello Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63251 to look at the new patch set (#10). Change subject: coreboot tables: Add PCIe info to coreboot table ...................................................................... coreboot tables: Add PCIe info to coreboot table Add 'pcie_fill_lb' and 'lb_add_pcie' functions to pass PCIe information from coreboot to libpayload. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller, configuration space and address translation unit for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63251/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 10 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t
by Jianjun Wang (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Hung-Te Lin, Jakub Czapiga, Yu-Ping Wu, Jianjun Wang. Hello Hung-Te Lin, Jakub Czapiga, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63494 to look at the new patch set (#2). Change subject: coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t ...................................................................... coreboot_tables: Convert 'struct lb_uint64' to lb_uint64_t Convert 'struct lb_uint64' to 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a --- M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/bootmem.c M src/lib/coreboot_table.c M tests/lib/bootmem-test.c M tests/lib/coreboot_table-test.c M util/cbmem/cbmem.c M util/nvramtool/coreboot_tables.h M util/nvramtool/lbtable.c 8 files changed, 37 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/63494/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 2 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Balaji Manigandan (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Jakub Czapiga, Selma Bensaid, Tim Wawrzynczak, Julius Werner. Balaji Manigandan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 02:01:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/defconfig: enable vboot Lib Build
by Selma Bensaid (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Bora Guvendik, Anil Kumar K, Jakub Czapiga, Tim Wawrzynczak, Julius Werner, Balaji Manigandan. Selma Bensaid has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: libpayload/defconfig: enable vboot Lib Build ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63240/comment/b5bad7c6_f8a84b84 PS3, Line 9: #3461454 > Tim, I update the commit. Hope this what you meant. […] Done Patchset: PS5: Tim I update the commit-msg -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Sat, 09 Apr 2022 01:59:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jakub Czapiga <jacz(a)semihalf.com> Comment-In-Reply-To: Selma Bensaid <selma.bensaid(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/qualcomm/common: Make clock_configure() check for exact matches
by Shelley Chen (Code Review) 09 Apr '22

09 Apr '22

Attention is currently required from: Taniya Das, Paul Menzel, Julius Werner. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63289 ) Change subject: soc/qualcomm/common: Make clock_configure() check for exact matches ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: Ummm.... is OCP_DELTALAKE_CBNT a newly added board? I don't think that anything that I've touched should cause it to fail building.... -- To view, visit https://review.coreboot.org/c/coreboot/+/63289 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cfad7236241f4d03ff1a56683654649658b68fc Gerrit-Change-Number: 63289 Gerrit-PatchSet: 10 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Sat, 09 Apr 2022 01:10:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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