coreboot-gerrit April 2022

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Change in coreboot[master]: mb/hp/t620: Add new mainboard HP T620 thin client
by Damien Zammit (Code Review) 10 Apr '22

10 Apr '22

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63519 ) Change subject: mb/hp/t620: Add new mainboard HP T620 thin client ...................................................................... mb/hp/t620: Add new mainboard HP T620 thin client This commit adds support for HP T620, work was done during a coreboot hacking party! Board is AMD Fam16kb with laptop ram. Based off biostar/a68n-5200 port. coreboot console works over serial COMA by default. Board is fanless, so no need for fan control. TESTED: Boots SeaBIOS and to linux, NIC works, serial works. Missing: - Audio verb table - PIRQs could be wrong (copied from other board) - ACPI could be wrong (copied from other board) Caveat: Without VGA ROM there are no displays. Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/mainboard/hp/t620/BiosCallOuts.c A src/mainboard/hp/t620/Kconfig A src/mainboard/hp/t620/Kconfig.name A src/mainboard/hp/t620/Makefile.inc A src/mainboard/hp/t620/OemCustomize.c A src/mainboard/hp/t620/OptionsIds.h A src/mainboard/hp/t620/acpi/AmdImc.asl A src/mainboard/hp/t620/acpi/gpe.asl A src/mainboard/hp/t620/acpi/mainboard.asl A src/mainboard/hp/t620/acpi/routing.asl A src/mainboard/hp/t620/acpi/sata.asl A src/mainboard/hp/t620/acpi/sleep.asl A src/mainboard/hp/t620/acpi/superio.asl A src/mainboard/hp/t620/acpi/thermal.asl A src/mainboard/hp/t620/acpi/usb_oc.asl A src/mainboard/hp/t620/board_info.txt A src/mainboard/hp/t620/bootblock.c A src/mainboard/hp/t620/buildOpts.c A src/mainboard/hp/t620/cmos.layout A src/mainboard/hp/t620/devicetree.cb A src/mainboard/hp/t620/dsdt.asl A src/mainboard/hp/t620/irq_tables.c A src/mainboard/hp/t620/mainboard.c 23 files changed, 1,092 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63519/1 diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c new file mode 100644 index 0000000..a0ac3f0 --- /dev/null +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <FchPlatform.h> + +const BIOS_CALLOUT_STRUCT BiosCallouts[] = +{ + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } +}; +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + +/** + * AMD Olivehill Platform ALC272 Verb Table + */ +static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { + {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST OlivehillCodecTableList[] = +{ + {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, + {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ + FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; + FchParams_reset->QeEnabled = FALSE; +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) +{ + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); +} diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig new file mode 100644 index 0000000..f897bab --- /dev/null +++ b/src/mainboard/hp/t620/Kconfig @@ -0,0 +1,41 @@ +if BOARD_HP_T620 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select CPU_AMD_AGESA_FAMILY16_KB + select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB + select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select SUPERIO_ASPEED_AST2400 + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config MAINBOARD_DIR + default "hp/t620" + +config MAINBOARD_PART_NUMBER + default "T620" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config HUDSON_LEGACY_FREE + bool + default n + +endif # BOARD_HP_T620 diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name new file mode 100644 index 0000000..fd55b76 --- /dev/null +++ b/src/mainboard/hp/t620/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_T620 + bool "T620" diff --git a/src/mainboard/hp/t620/Makefile.inc b/src/mainboard/hp/t620/Makefile.inc new file mode 100644 index 0000000..549801d --- /dev/null +++ b/src/mainboard/hp/t620/Makefile.inc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += buildOpts.c +romstage-y += BiosCallOuts.c +romstage-y += OemCustomize.c + +ramstage-y += buildOpts.c +ramstage-y += BiosCallOuts.c +ramstage-y += OemCustomize.c diff --git a/src/mainboard/hp/t620/OemCustomize.c b/src/mainboard/hp/t620/OemCustomize.c new file mode 100644 index 0000000..18db540 --- /dev/null +++ b/src/mainboard/hp/t620/OemCustomize.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> +#include <PlatformMemoryConfiguration.h> + +#include <northbridge/amd/agesa/state_machine.h> + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x01, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x05, 0) + } +}; + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 to HDMI0/DP */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 to FCH */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 to HDMI1/DP */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeCrt, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortList, + .DdiLinkList = DdiList +}; + +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = FALSE; +} + +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; +} + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERRIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { + #define SEED_A 0x12 + HW_RXEN_SEED( + ANY_SOCKET, CHANNEL_A, ALL_DIMMS, + SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, + SEED_A), + + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + MOTHER_BOARD_LAYERS(LAYERS_4), + + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + + PSO_END +}; + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/hp/t620/OptionsIds.h b/src/mainboard/hp/t620/OptionsIds.h new file mode 100644 index 0000000..130d852 --- /dev/null +++ b/src/mainboard/hp/t620/OptionsIds.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +//#define IDSOPT_TRACING_ENABLED TRUE +#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE + +#endif diff --git a/src/mainboard/hp/t620/acpi/AmdImc.asl b/src/mainboard/hp/t620/acpi/AmdImc.asl new file mode 100644 index 0000000..4483834 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/AmdImc.asl @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//BTDC Due to IMC Fan, ACPI control codes +OperationRegion(IMIO, SystemIO, 0x3E, 0x02) +Field(IMIO , ByteAcc, NoLock, Preserve) { + IMCX,8, + IMCA,8 +} + +IndexField(IMCX, IMCA, ByteAcc, NoLock, Preserve) { + Offset(0x80), + MSTI, 8, + MITS, 8, + MRG0, 8, + MRG1, 8, + MRG2, 8, + MRG3, 8, +} + +Method(WACK, 0) +{ + Local0 = 0 + While (Local0 != 0xfa) { + Local0 = MRG0 + Sleep(10) + } +} + +//Init +Method (ITZE, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 + WACK() + + Local0 = MRG2 | 0x01 + + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 + WACK() +} + +//Sleep +Method (IMSP, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 1 + MRG2 = 0 + MSTI = 0x98 + WACK() + + MRG0 = 0 + MRG1 = 0xb4 + MRG2 = 0 + MSTI = 0x96 + WACK() +} + +//Wake +Method (IMWK, 0) +{ + MRG0 = 0 + MRG1 = 0xb5 + MRG2 = 0 + MSTI = 0x96 + WACK() + + MRG0 = 0 + MRG1 = 0 + MRG2 = 0 + MSTI = 0x80 + WACK() + + Local0 = MRG2 | 0x01 + + MRG0 = 0 + MRG1 = 0 + MRG2 = Local0 + MSTI = 0x81 + WACK() +} diff --git a/src/mainboard/hp/t620/acpi/gpe.asl b/src/mainboard/hp/t620/acpi/gpe.asl new file mode 100644 index 0000000..778c7f7 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/gpe.asl @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/hp/t620/acpi/mainboard.asl b/src/mainboard/hp/t620/acpi/mainboard.asl new file mode 100644 index 0000000..9b18e72 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/mainboard.asl @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +/* AcpiGpe0Blk */ +OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, +} diff --git a/src/mainboard/hp/t620/acpi/routing.asl b/src/mainboard/hp/t620/acpi/routing.asl new file mode 100644 index 0000000..9bce4b2 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/routing.asl @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F16 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 44 }, + Package(){0x0001FFFF, 1, 0, 45 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 24 }, + Package(){0x0002FFFF, 1, 0, 25 }, + Package(){0x0002FFFF, 2, 0, 26 }, + Package(){0x0002FFFF, 3, 0, 27 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + /* Bus 0, Dev 18, 19, 22 Func 1 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + +}) + +Name(PS2, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS2, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, +}) + +/* GFX */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 0 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 1 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 3 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/hp/t620/acpi/sata.asl b/src/mainboard/hp/t620/acpi/sata.asl new file mode 100644 index 0000000..659a076 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/sata.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* No SATA functionality */ diff --git a/src/mainboard/hp/t620/acpi/sleep.asl b/src/mainboard/hp/t620/acpi/sleep.asl new file mode 100644 index 0000000..fc26c30 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/sleep.asl @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ + +External(\_SB.APTS, MethodObj) +External(\_SB.AWAK, MethodObj) + +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + WKST [0] = 0 + WKST [1] = 0 + UPWS = 7 + \_SB.APTS(Arg0) +} /* End Method(\_PTS) */ + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + USBS = 1 + + \_SB.AWAK(Arg0) + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/hp/t620/acpi/superio.asl b/src/mainboard/hp/t620/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/superio.asl diff --git a/src/mainboard/hp/t620/acpi/thermal.asl b/src/mainboard/hp/t620/acpi/thermal.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/t620/acpi/thermal.asl diff --git a/src/mainboard/hp/t620/acpi/usb_oc.asl b/src/mainboard/hp/t620/acpi/usb_oc.asl new file mode 100644 index 0000000..a5846fe --- /dev/null +++ b/src/mainboard/hp/t620/acpi/usb_oc.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt new file mode 100644 index 0000000..4132ada --- /dev/null +++ b/src/mainboard/hp/t620/board_info.txt @@ -0,0 +1,2 @@ +Category: eval +Socketed Flash: Y diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c new file mode 100644 index 0000000..f77d6e0 --- /dev/null +++ b/src/mainboard/hp/t620/bootblock.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <stdint.h> +#include <device/pci_ops.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> + +#define SERIAL_DEV PNP_DEV(0x2e, AST2400_SUART2) + +#if 0 +static void sbxxx_enable_48mhzout(void) +{ + u32 reg32; + + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + reg32 = misc_read32(0x28); + reg32 &= 0xfff8ffff; + misc_write32(0x28, reg32); + + /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + reg32 = misc_read32(0x40); + reg32 &= 0xffffbffb; + misc_write32(0x40, reg32); +} +#endif + +void bootblock_mainboard_early_init(void) +{ + u8 byte; + + /* Enable the AcpiMmio space */ + pm_io_write8(0x24, 1); + + /* Set LPC decode enables. */ + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffc0); + + /* enable SIO LPC decode */ + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + /* enable SIO clock */ + //ASSUME CLOCK IS CORRECT sbxxx_enable_48mhzout(); + + /* Enable serial output on it8728f */ + aspeed_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/hp/t620/buildOpts.c b/src/mainboard/hp/t620/buildOpts.c new file mode 100644 index 0000000..f5c2181 --- /dev/null +++ b/src/mainboard/hp/t620/buildOpts.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <AGESA.h> + +#define INSTALL_FT3_SOCKET_SUPPORT TRUE +#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE + +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CDIT TRUE + +/* Build configuration values here. */ +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE + +#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_IOMMU_SUPPORT FALSE + +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE + +/* Include the files that instantiate the configuration definitions. */ +#include "cpuRegisters.h" +#include "cpuFamRegisters.h" +#include "cpuFamilyTranslation.h" +#include "AdvancedApi.h" +#include "heapManager.h" +#include "CreateStruct.h" +#include "cpuFeatures.h" +#include "Table.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "GnbInterface.h" + +#include <PlatformInstall.h> diff --git a/src/mainboard/hp/t620/cmos.layout b/src/mainboard/hp/t620/cmos.layout new file mode 100644 index 0000000..a11e1dd --- /dev/null +++ b/src/mainboard/hp/t620/cmos.layout @@ -0,0 +1,35 @@ +#***************************************************************************** +# SPDX-License-Identifier: GPL-2.0-only + +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +444 1 e 1 nmi +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb new file mode 100644 index 0000000..ed6fa58 --- /dev/null +++ b/src/mainboard/hp/t620/devicetree.cb @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x103c 0x2187 inherit + chip northbridge/amd/agesa/family16kb + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal HDMI Audio + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 off end + device pci 2.2 on end + device pci 2.3 on end + device pci 2.4 off end # Edge Connector + device pci 2.5 off end # Edge Connector + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SMBus + device pci 14.2 on end # Audio Azalia + device pci 14.3 on # LPC + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "0" + device pnp 2e.2 off end # SUART1 + device pnp 2e.3 on # SUART2 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0x71 = 3 + irq 0xf0 = 2 + end + end + end + end + end #LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/agesa/hudson + + chip northbridge/amd/agesa/family16kb + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = "{ + { {0xA0, 0xA2}, {0x00, 0x00}, }, + { {0x00, 0x00}, {0x00, 0x00}, }, + }" + end + end +end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/t620/dsdt.asl b/src/mainboard/hp/t620/dsdt.asl new file mode 100644 index 0000000..c86cf27 --- /dev/null +++ b/src/mainboard/hp/t620/dsdt.asl @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + #include <acpi/dsdt_top.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> + + /* Describe the processor tree (\_SB) */ + #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <southbridge/amd/common/acpi/sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/fch.asl> + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/hp/t620/irq_tables.c b/src/mainboard/hp/t620/irq_tables.c new file mode 100644 index 0000000..6d75c05 --- /dev/null +++ b/src/mainboard/hp/t620/irq_tables.c @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <string.h> +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "%s done.\n", __func__); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/hp/t620/mainboard.c b/src/mainboard/hp/t620/mainboard.c new file mode 100644 index 0000000..3ebc0c1 --- /dev/null +++ b/src/mainboard/hp/t620/mainboard.c @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <southbridge/amd/common/amd_pci_util.h> + +static const u8 mainboard_picr_data[0x54] = { + 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x04, 0x05, 0x07 +}; +static const u8 mainboard_intr_data[0x54] = { + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/********************************************** + * enable the dedicated function in mainboard. + **********************************************/ +static void mainboard_enable(struct device *dev) +{ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/63519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 63519 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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Change in em100[master]: makechips.sh: Reformat script with shfmt
by Stefan Reinauer (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Martin Roth. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/em100/+/62939 ) Change subject: makechips.sh: Reformat script with shfmt ...................................................................... Patch Set 1: Code-Review+1 (3 comments) File makechips.sh: https://review.coreboot.org/c/em100/+/62939/comment/4f2205f6_6f25747f PS1, Line 17: if ! which curl >/dev/null; then : echo "Install curl to run this script." : exit 1 : fi : if ! which msiextract >/dev/null; then : echo "Install msitools (https://wiki.gnome.org/msitools) to run this script." : exit 1 : fi : For some reason gerrit is removing ALL spaces from the above lines https://review.coreboot.org/c/em100/+/62939/comment/1eb68cd7_3aa6ffd9 PS1, Line 28: WD="$( : cd "$(dirname "$(eval echo "$0")")" || exit 1 : pwd : )" Why split this one up, .... https://review.coreboot.org/c/em100/+/62939/comment/ea693d58_d6ad3174 PS1, Line 52: VERSION="$(strings -e l Program\ Files/DediProg/EM100/EM100.exe | grep -A1 ProductVersion | grep EM100)" ... but not this one. (I know the answer, but it doesn't seem to make much sense) -- To view, visit https://review.coreboot.org/c/em100/+/62939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I92c1044f93e0322fe13ea3804371203e321293d9 Gerrit-Change-Number: 62939 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 03:56:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in em100[master]: makechips.sh: Build makedpfw if not present
by Stefan Reinauer (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Martin Roth. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/em100/+/62938 ) Change subject: makechips.sh: Build makedpfw if not present ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/em100/+/62938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: If5dd121a4977126c456162de7d4328d69e741902 Gerrit-Change-Number: 62938 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 03:52:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in em100[master]: makechips.sh: Clean up shellcheck errors and formatting
by Stefan Reinauer (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Martin Roth. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/em100/+/62937 ) Change subject: makechips.sh: Clean up shellcheck errors and formatting ...................................................................... Patch Set 1: (6 comments) File makechips.sh: https://review.coreboot.org/c/em100/+/62937/comment/e998b478_b53b5a92 PS1, Line 33: FILE ${FILE}? https://review.coreboot.org/c/em100/+/62937/comment/e84f82f1_2577007a PS1, Line 36: FILE ${FILE}? https://review.coreboot.org/c/em100/+/62937/comment/fc8c2a96_11f6e74b PS1, Line 37: URL ${URL}? ${FILE}? https://review.coreboot.org/c/em100/+/62937/comment/c55b0812_5e9348db PS1, Line 40: FILE ${FILE} ? https://review.coreboot.org/c/em100/+/62937/comment/f6dbac1e_7e28176e PS1, Line 46: VERSION should this be ${VERSION} ? https://review.coreboot.org/c/em100/+/62937/comment/187cf0af_b63a7f30 PS1, Line 57: i ${i} ? -- To view, visit https://review.coreboot.org/c/em100/+/62937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ia756d67d0a0464971e395189027b01787b6b19bd Gerrit-Change-Number: 62937 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 03:51:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: IASL: Correct warning message for IASL missing dependency
by Elyes Haouas (Code Review) 10 Apr '22

10 Apr '22

Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63250 ) Change subject: IASL: Correct warning message for IASL missing dependency ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: please see https://github.com/acpica/acpica/blob/master/documents/changes.txt line 186 -- To view, visit https://review.coreboot.org/c/coreboot/+/63250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be740354b159e931e41323aef14e160cc09af19 Gerrit-Change-Number: 63250 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 01:25:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/haswell: Rename mainboard.c to ramstage.c
by build bot (Jenkins) (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Alexander Couzens. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63512 ) Change subject: mb/lenovo/haswell: Rename mainboard.c to ramstage.c ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bc60b30f104f6bf483d79332bcd6d5f090d585f Gerrit-Change-Number: 63512 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 10 Apr 2022 00:39:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo: Rename t440p to haswell
by build bot (Jenkins) (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Alexander Couzens. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63511 ) Change subject: mb/lenovo: Rename t440p to haswell ...................................................................... Patch Set 2: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9d68d54d5f0821bbf85faaa620855d456c97f3 Gerrit-Change-Number: 63511 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 10 Apr 2022 00:24:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/t440p/dsdt.asl: Remove redundant comment
by Felix Singer (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Paul Menzel, Alexander Couzens. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63428 ) Change subject: mb/lenovo/t440p/dsdt.asl: Remove redundant comment ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63428/comment/0a1fd2d6_93c07a60 PS1, Line 7: unuseful > redundant Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie772701192a3589b51642df446f0b2527fb7d630 Gerrit-Change-Number: 63428 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 10 Apr 2022 00:19:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/haswell: Rename mainboard.c to ramstage.c
by Felix Singer (Code Review) 10 Apr '22

10 Apr '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63512 ) Change subject: mb/lenovo/haswell: Rename mainboard.c to ramstage.c ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/63512 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bc60b30f104f6bf483d79332bcd6d5f090d585f Gerrit-Change-Number: 63512 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Apr 2022 00:09:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo: Rename t440p to haswell
by Felix Singer (Code Review) 10 Apr '22

10 Apr '22

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63511 ) Change subject: mb/lenovo: Rename t440p to haswell ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/63511 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a9d68d54d5f0821bbf85faaa620855d456c97f3 Gerrit-Change-Number: 63511 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Apr 2022 00:08:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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