coreboot-gerrit April 2022

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Change in coreboot[master]: mb/hp/t620: Add clone of biostar/a68n-5200
by Damien Zammit (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Damien Zammit. Hello Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63519 to look at the new patch set (#2). Change subject: mb/hp/t620: Add clone of biostar/a68n-5200 ...................................................................... mb/hp/t620: Add clone of biostar/a68n-5200 HP T620 was ported to coreboot based on the biostar/a68n-5200 port. This commit is a direct clone of the previous board, with the name changed to make it pass jenkins. Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- A src/mainboard/hp/t620/BiosCallOuts.c A src/mainboard/hp/t620/Kconfig A src/mainboard/hp/t620/Kconfig.name A src/mainboard/hp/t620/Makefile.inc A src/mainboard/hp/t620/OemCustomize.c A src/mainboard/hp/t620/OptionsIds.h A src/mainboard/hp/t620/acpi/AmdImc.asl A src/mainboard/hp/t620/acpi/gpe.asl A src/mainboard/hp/t620/acpi/mainboard.asl A src/mainboard/hp/t620/acpi/routing.asl A src/mainboard/hp/t620/acpi/sata.asl A src/mainboard/hp/t620/acpi/sleep.asl A src/mainboard/hp/t620/acpi/superio.asl A src/mainboard/hp/t620/acpi/thermal.asl A src/mainboard/hp/t620/acpi/usb_oc.asl A src/mainboard/hp/t620/board_info.txt A src/mainboard/hp/t620/bootblock.c A src/mainboard/hp/t620/buildOpts.c A src/mainboard/hp/t620/cmos.layout A src/mainboard/hp/t620/devicetree.cb A src/mainboard/hp/t620/dsdt.asl A src/mainboard/hp/t620/irq_tables.c A src/mainboard/hp/t620/mainboard.c 23 files changed, 1,242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63519/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 63519 Gerrit-PatchSet: 2 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/prodrive/atlas: Update KConfig
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Christian Walter, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63464 ) Change subject: mb/prodrive/atlas: Update KConfig ...................................................................... Patch Set 4: (3 comments) File src/mainboard/prodrive/atlas/Kconfig: https://review.coreboot.org/c/coreboot/+/63464/comment/8bcb8e9b_dbb3c8fe PS2, Line 5: select DRIVERS_I2C_GENERIC : select DRIVERS_INTEL_DPTF : select DRIVERS_SPI_ACPI : select DRIVERS_USB_ACPI > Yes actually all of these have been enabled in devicetree: […] But the chip drivers aren't used. For `DRIVERS_USB_ACPI`, the devicetree should have something like this: device ref xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" device ref xhci_root_hub on chip drivers/usb/acpi register "desc" = ""Bluetooth"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port10 on end end end end end But I don't see any `chip drivers/usb/acpi` or similar in Atlas' devicetree. https://review.coreboot.org/c/coreboot/+/63464/comment/20cd12a1_7f2397d9 PS2, Line 9: select DRIVERS_UART_8250IO > Because the current main debug UART we are using now is the EC UART. […] Ah, I see. I guess no setup is required because the EC autoconfigures the UART's I/O base address to 0x3f8, is my guess correct? https://review.coreboot.org/c/coreboot/+/63464/comment/c9d87604_855e67e5 PS2, Line 17: : config IGNORE_IASL_MISSING_DEPENDENCY : def_bool y > This is the common problem with IASL error for all ADL platforms. Hmmm, looks like it's a problem with ChromeOS ASL. When building for ADLRVP-P with Intel EC, this is not a problem. -- To view, visit https://review.coreboot.org/c/coreboot/+/63464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Gerrit-Change-Number: 63464 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 08:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Sridhar Siricilla, Kane Chen. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 ) Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/soc/intel/alderlake/chip.h: https://review.coreboot.org/c/coreboot/+/63293/comment/7eadba4d_117bedd4 PS7, Line 578: * Add Workaround to disable PCH USB2 Phy power gating as per Intel TA# 723158 to : * prevent possible display flicker issue. : * Enable or Disable PCH USB2 Phy power gating. : * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. > > unrelated to the TA ? […] I suggested mentioning the TA here in case someone doesn't see the help text in mainboard code. But I'd reword this a bit: /* * Enable or Disable PCH USB2 Phy power gating. * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. * Workaround for Intel TA# 723158 to prevent possible display flicker. */ Or something like this. Even `Related to Intel TA# 723158` could work. -- To view, visit https://review.coreboot.org/c/coreboot/+/63293 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Gerrit-Change-Number: 63293 Gerrit-PatchSet: 7 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 07:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: IASL: Correct warning message for IASL missing dependency
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63250 ) Change subject: IASL: Correct warning message for IASL missing dependency ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I think Elyes is referring to this part: > iASL compiler: Updated the check for usage of _CRS, _DIS, _PRS, and _SRS objects: > New/latest rules: Under a Device Object: > 1) If _PRS is present, must have _CRS and _SRS > 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS) > 3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS) > 4) If _SRS is present, probably should have a _DIS (Remark only) AIUI, our messages state the same as points 1, 2 and 3, but more succintly (we don't mention the entire dependency chain) -- To view, visit https://review.coreboot.org/c/coreboot/+/63250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be740354b159e931e41323aef14e160cc09af19 Gerrit-Change-Number: 63250 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 07:36:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/common: Move RAM calculation to common code
by Paul Menzel (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Nico Huber, Michał Żygowski. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61682 ) Change subject: nb/amd/common: Move RAM calculation to common code ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61682/comment/ac7c9fac_5fbebbb4 PS4, Line 12: did do File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/61682/comment/16983fc7_fef2268a PS4, Line 525: u64 basek, limitk, sizek; // 4 1T Please add a comment about the type changes in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/61682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d222f6cbd26fe78d968d2883984f25e8b62ab5c Gerrit-Change-Number: 61682 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 05:26:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/amd/agesa/family14/northbridge.c: Report missing resources
by Paul Menzel (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Nico Huber, Michał Żygowski, Michał Kopeć, Angel Pons, Felix Held. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52935 ) Change subject: nb/amd/agesa/family14/northbridge.c: Report missing resources ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52935/comment/58eb2507_f3229f4c PS9, Line 9: Not all resources were being reported, add them. Which ones exactly? File src/northbridge/amd/agesa/family14/northbridge.c: https://review.coreboot.org/c/coreboot/+/52935/comment/b2f630e4_d1ff8241 PS9, Line 115: /* Reserve everything between A segment and 1MB: Please use: /* * […] */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b1b5f585ff6e0c7aecad250a75600e0c76331e1 Gerrit-Change-Number: 52935 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 10 Apr 2022 05:22:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: southbridge/amd: Unify smbus.{c,h} and make them common
by Paul Menzel (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61890 ) Change subject: southbridge/amd: Unify smbus.{c,h} and make them common ...................................................................... Patch Set 4: (1 comment) File src/southbridge/amd/common/smbus.h: https://review.coreboot.org/c/coreboot/+/61890/comment/8079353f_021a2288 PS4, Line 27: #define AX_INDXC 0 > Strange, as `src/southbridge/amd/cimx/sb800/smbus.h` also defines macros using this define: […] Some archaeology: Commit 63e62b03a8 (This code provides southbridge initialization for SB800 south bridges. It is dependent on the AMD CIMx/SB800 code.) adds the macros, but they are commented out. /*//SB00.H #define AX_INDXC 0 #define AX_INDXP 2 #define AXCFG 4 #define ABCFG 6 #define RC_INDXC 1 #define RC_INDXP 3 */ Then commit 0141f0d6b8 (sb/amd/*/*/smbus.h: Make 'smbus.h' uniform) remove the commented out section, but misses to comment, that the macros are actually referenced further down. -- To view, visit https://review.coreboot.org/c/coreboot/+/61890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef8e4168b470435b244844e41ddb7f564bddf65 Gerrit-Change-Number: 61890 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin Roth <martin.roth(a)tinkermill.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 10 Apr 2022 05:14:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/t620: Add new mainboard HP T620 thin client
by Paul Menzel (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Damien Zammit. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63519 ) Change subject: mb/hp/t620: Add new mainboard HP T620 thin client ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63519/comment/cba7f069_fffcacc2 PS1, Line 9: This commit adds support for HP T620, work was done : during a coreboot hacking party! : Board is AMD Fam16kb with laptop ram. Based off biostar/a68n-5200 port. Please reflow for 72 characters per line. https://review.coreboot.org/c/coreboot/+/63519/comment/7f0b90d1_46357b83 PS1, Line 16: SeaBIOS Which version? https://review.coreboot.org/c/coreboot/+/63519/comment/2f18b804_5e24d6da PS1, Line 16: linux Which version? https://review.coreboot.org/c/coreboot/+/63519/comment/24e4d6e4_24959b7f PS1, Line 23: Caveat: Without VGA ROM there are no displays. Is coreboot able to execute it too, or does it only work with SeaBIOS? https://review.coreboot.org/c/coreboot/+/63519/comment/f772f657_40d7d9ad PS1, Line 23: VGA ROM 1. Video/VGA BIOS Option ROM 2. What version did you extract and test with? Patchset: PS1: It’s hard to review, as it’s unclear what stuff is copied, and what was adapted. -- To view, visit https://review.coreboot.org/c/coreboot/+/63519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 63519 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Comment-Date: Sun, 10 Apr 2022 04:30:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: IASL: Correct warning message for IASL missing dependency
by Paul Menzel (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Frans Hendriks. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63250 ) Change subject: IASL: Correct warning message for IASL missing dependency ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > please see https://github.com/acpica/acpica/blob/master/documents/changes. […] ``` iasl: Check usage of _CRS, _DIS, _PRS, and _SRS objects (July 2021). Under the Device Object: 1) If _DIS is present, must have a _CRS and _SRS 2) If _PRS is present, must have a _CRS, _DIS, and _SRS 3) If _SRS is present, must have a _CRS and _DIS A warning will be issued for each of these cases. Note: For existing ASL/projects, these warnings may be disabled by specifying this on the command line: "-vw 3141" ``` Is your comment with the reference meant as confirmation, or is there something wrong with the commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/63250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1be740354b159e931e41323aef14e160cc09af19 Gerrit-Change-Number: 63250 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 04:26:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/t620: Add new mainboard HP T620 thin client
by build bot (Jenkins) (Code Review) 10 Apr '22

10 Apr '22

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63519 ) Change subject: mb/hp/t620: Add new mainboard HP T620 thin client ...................................................................... Patch Set 1: (24 comments) File src/mainboard/hp/t620/BiosCallOuts.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/1c90b372_99152696 PS1, Line 9: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/0e318e71_5c7b08ae PS1, Line 29: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/fce38cfc_d76c15a2 PS1, Line 30: {0x10ec0272, (CODEC_ENTRY*)&Olivehill_Alc272_VerbTbl[0]}, "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/c2064106_4c96d729 PS1, Line 31: {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} "(foo*)" should be "(foo *)" Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/2e15cf3c_a0f210b8 PS1, Line 43: FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); line over 96 characters File src/mainboard/hp/t620/OemCustomize.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/af7abb1d_96e0b635 PS1, Line 118: NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/3a591788_8d6ae821 PS1, Line 119: NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/e132cfac_be62ca92 PS1, Line 120: MOTHER_BOARD_LAYERS(LAYERS_4), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/097c9d43_eb7cad42 PS1, Line 122: MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/0e8491aa_3778a37e PS1, Line 123: CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/3db4bceb_ad558ff4 PS1, Line 124: ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/75c23b44_8eeeca1e PS1, Line 125: CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/3b80fd96_165bc1a0 PS1, Line 127: PSO_END please, no spaces at the start of a line File src/mainboard/hp/t620/irq_tables.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/ae949e8f_9e68956a PS1, Line 81: if (sum != pirq->checksum) { braces {} are not necessary for single statement blocks File src/mainboard/hp/t620/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/33e5eb57_316f57b2 PS1, Line 7: 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/43e092aa_9fd29968 PS1, Line 8: 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/94f197c5_18a8107e PS1, Line 9: 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/9392950f_4532f568 PS1, Line 10: 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/e1a8984a_f31e7016 PS1, Line 11: 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/74a90f45_399c63f7 PS1, Line 15: 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/fe495f7a_188d1a20 PS1, Line 16: 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/7db205f5_a3f20d88 PS1, Line 17: 0x05, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/6911270d_a74a8a8d PS1, Line 18: 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-145981): https://review.coreboot.org/c/coreboot/+/63519/comment/f7418f6b_e605875b PS1, Line 19: 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5d195de19b83360307f154e4b9cb974e5d5c5ec Gerrit-Change-Number: 63519 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Apr 2022 04:08:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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