coreboot-gerrit April 2022

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Change in coreboot[master]: superio/smsc/sch5545: Drop `_PRS` from static devices
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Michał Żygowski, Michał Kopeć, Felix Held. Hello Michał Żygowski, Michał Kopeć, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63522 to look at the new patch set (#2). Change subject: superio/smsc/sch5545: Drop `_PRS` from static devices ...................................................................... superio/smsc/sch5545: Drop `_PRS` from static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only mainboard using the SCH5545 code, `dell/snb_ivb_workstations`. Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/superio/smsc/sch5545/acpi/superio.asl 2 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63522/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Gerrit-Change-Number: 63522 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/google/chromeec: Drop `_PRS` from static devices
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Felix Held. Hello Subrata Banik, Tim Wawrzynczak, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63521 to look at the new patch set (#2). Change subject: ec/google/chromeec: Drop `_PRS` from static devices ...................................................................... ec/google/chromeec: Drop `_PRS` from static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 0 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63521/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c Gerrit-Change-Number: 63521 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Add a common romstage entry
by Nico Huber (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Jason Glenesk, Furquan Shaikh, Marshall Dawson, Angel Pons, Arthur Heymans, Fred Reitberger, Patrick Rudolph, Felix Held. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55067 ) Change subject: arch/x86: Add a common romstage entry ...................................................................... Patch Set 13: Code-Review+1 (1 comment) File src/cpu/intel/car/romstage.c: https://review.coreboot.org/c/coreboot/+/55067/comment/ecae3445_a7b0d25e PS13, Line 58: /* We do not return here. */ : die("failed to load postcar\n"); : Shouldn't we move this to common code too? -- To view, visit https://review.coreboot.org/c/coreboot/+/55067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f Gerrit-Change-Number: 55067 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 10 Apr 2022 09:04:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: superio/smsc/mec1308: Drop `_PRS` for static devices
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63523 ) Change subject: superio/smsc/mec1308: Drop `_PRS` for static devices ...................................................................... superio/smsc/mec1308: Drop `_PRS` for static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the two mainboards using the MEC1308 code, `samsung/{lumpy, stumpy}`. Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/superio/smsc/mec1308/acpi/superio.asl 3 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/63523/1 diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index f9710e5..d0574bb 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -1,8 +1,5 @@ if BOARD_SAMSUNG_LUMPY -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 13b0eacbf..2a706b9 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -1,8 +1,5 @@ if BOARD_SAMSUNG_STUMPY -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index f692323..117de96 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -101,11 +101,6 @@ { IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) }) - - Name (_PRS, ResourceTemplate () - { - IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08) - }) } #endif @@ -122,11 +117,6 @@ { IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) }) - - Name (_PRS, ResourceTemplate () - { - IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04) - }) } #endif @@ -143,11 +133,6 @@ { IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) }) - - Name (_PRS, ResourceTemplate () - { - IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04) - }) } #endif @@ -165,12 +150,6 @@ IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) IRQNoFlags () {SIO_SSP1_IRQ} }) - - Name (_PRS, ResourceTemplate () - { - IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08) - IRQNoFlags () {SIO_SSP1_IRQ} - }) } #endif @@ -190,13 +169,6 @@ IO (Decode16, 0x64, 0x64, 0x01, 0x01) IRQNoFlags () {1} }) - - Name (_PRS, ResourceTemplate() - { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) - IRQNoFlags () {1} - }) } #endif @@ -213,11 +185,6 @@ { IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) }) - - Name (_PRS, ResourceTemplate () - { - IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04) - }) } #endif @@ -235,11 +202,6 @@ { IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x01, 0x34) }) - - Name (_PRS, ResourceTemplate() - { - IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x01, 0x34) - }) } #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/63523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d5cdc28c2cfaa5dfcffd656060b931208977386 Gerrit-Change-Number: 63523 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/smsc/sch5545: Drop `_PRS` for static devices
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63522 ) Change subject: superio/smsc/sch5545: Drop `_PRS` for static devices ...................................................................... superio/smsc/sch5545: Drop `_PRS` for static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. In addition, drop `IGNORE_IASL_MISSING_DEPENDENCY` from the only mainboard using the SCH5545 code, `dell/snb_ivb_workstations`. Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/dell/snb_ivb_workstations/Kconfig M src/superio/smsc/sch5545/acpi/superio.asl 2 files changed, 0 insertions(+), 28 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63522/1 diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig index 8416a0f..788f5a1 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -20,9 +20,6 @@ if BOARD_DELL_SNB_IVB_WORKSTATIONS -config IGNORE_IASL_MISSING_DEPENDENCY - def_bool y - config MAINBOARD_DIR default "dell/snb_ivb_workstations" diff --git a/src/superio/smsc/sch5545/acpi/superio.asl b/src/superio/smsc/sch5545/acpi/superio.asl index 97303c2..20278b4 100644 --- a/src/superio/smsc/sch5545/acpi/superio.asl +++ b/src/superio/smsc/sch5545/acpi/superio.asl @@ -232,22 +232,6 @@ ) IRQ (Edge, ActiveHigh, Exclusive) {1} }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0x00, 0x00) - { - FixedIO ( - 0x0060, // Address - 0x01, - ) - FixedIO ( - 0x0064, // Address - 0x01, - ) - IRQ (Edge, ActiveHigh, Exclusive) {1} - } - EndDependentFn () - }) Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake { KBFG = Arg0 @@ -268,15 +252,6 @@ IRQ (Edge, ActiveHigh, Exclusive) {12} }) - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0x00, 0x00) - { - IRQ (Edge, ActiveHigh, Exclusive) {12} - } - EndDependentFn () - }) - Method (_PSW, 1, NotSerialized) { MSFG = Arg0 -- To view, visit https://review.coreboot.org/c/coreboot/+/63522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic462bd3dfa287744d4f733561de81c09c1c397e6 Gerrit-Change-Number: 63522 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Restore `mainboard_early_init()` call
by Nico Huber (Code Review) 10 Apr '22

10 Apr '22

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63515 ) Change subject: nb/intel/sandybridge: Restore `mainboard_early_init()` call ...................................................................... nb/intel/sandybridge: Restore `mainboard_early_init()` call Commit 7a874330919a4df9cc5b66058b4340465b7ea041 (mb/google,samsung: Drop init_bootmode_straps()) got rid of the `mainboard_early_init()` function call and weak definition in Sandy Bridge code. However, this function is still used by several Sandy Bridge mainboards, so bring back the dropped call and weak definition. The aforementioned commit did not cause any build-time errors because it did not remove the `mainboard_early_init()` function declaration. Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63515 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/sandybridge/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 1b6e744..56dc677 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -16,6 +16,10 @@ #include <southbridge/intel/common/pmclib.h> #include <elog.h> +__weak void mainboard_early_init(int s3resume) +{ +} + __weak void mainboard_late_rcba_config(void) { } @@ -67,6 +71,8 @@ post_code(0x38); + mainboard_early_init(s3resume); + post_code(0x39); if (CONFIG(INTEL_TXT)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82768e9a187696d42b61be44d4aa048acc19d551 Gerrit-Change-Number: 63515 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/prodrive/atlas: Update KConfig
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Christian Walter, Lean Sheng Tan. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63464 ) Change subject: mb/prodrive/atlas: Update KConfig ...................................................................... Patch Set 4: (1 comment) File src/mainboard/prodrive/atlas/Kconfig: https://review.coreboot.org/c/coreboot/+/63464/comment/6141f98a_62bccc23 PS2, Line 17: : config IGNORE_IASL_MISSING_DEPENDENCY : def_bool y > Hmmm, looks like it's a problem with ChromeOS ASL. […] The ChromeOS ASL should be fixed by CB:63521 -- To view, visit https://review.coreboot.org/c/coreboot/+/63464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I970de724237bcb08899aed7a4b87a23c5cdb0b48 Gerrit-Change-Number: 63464 Gerrit-PatchSet: 4 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 10 Apr 2022 08:21:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Drop `_PRS` for static devices
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63521 ) Change subject: ec/google/chromeec: Drop `_PRS` for static devices ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This should allow dropping the `IGNORE_IASL_MISSING_DEPENDENCY` Kconfig symbol from ChromeOS boards. -- To view, visit https://review.coreboot.org/c/coreboot/+/63521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c Gerrit-Change-Number: 63521 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 10 Apr 2022 08:21:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google/chromeec: Drop `_PRS` for static devices
by Angel Pons (Code Review) 10 Apr '22

10 Apr '22

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63521 ) Change subject: ec/google/chromeec: Drop `_PRS` for static devices ...................................................................... ec/google/chromeec: Drop `_PRS` for static devices The `_PRS` ACPI object is not needed for static (non-configurable) devices. For devices where `_CRS` always provides the same set of resource settings, drop the `_PRS` object. Note that every dropped `_PRS` object only provides one set of resource settings, which is identical to the resource settings provided by the `_CRS` object. Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/google/chromeec/acpi/superio.asl 1 file changed, 0 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63521/1 diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl index 05310be..0620e09 100644 --- a/src/ec/google/chromeec/acpi/superio.asl +++ b/src/ec/google/chromeec/acpi/superio.asl @@ -37,12 +37,6 @@ IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP, 0x08, EC_MEMMAP_SIZE) }) - - Name (_PRS, ResourceTemplate () - { - IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP, - 0x08, EC_MEMMAP_SIZE) - }) } #endif @@ -70,23 +64,6 @@ EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, 0x08, EC_HOST_CMD_REGION_SIZE) }) - - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0, 0) { - IO (Decode16, EC_LPC_ADDR_HOST_DATA, - EC_LPC_ADDR_HOST_DATA, 0x01, 0x01) - IO (Decode16, EC_LPC_ADDR_HOST_CMD, - EC_LPC_ADDR_HOST_CMD, 0x01, 0x01) - IO (Decode16, - EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, - 0x08, EC_HOST_CMD_REGION_SIZE) - IO (Decode16, - EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, - 0x08, EC_HOST_CMD_REGION_SIZE) - } - EndDependentFn () - }) } #endif @@ -104,15 +81,6 @@ IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) IRQNoFlags () {4} }) - - Name (_PRS, ResourceTemplate () - { - StartDependentFn (0, 0) { - IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) - IRQNoFlags () {4} - } - EndDependentFn () - }) } #endif } @@ -140,20 +108,6 @@ IRQ (Edge, ActiveHigh, Exclusive) {1} #endif }) - - Name (_PRS, ResourceTemplate() - { - StartDependentFn (0, 0) { - IO (Decode16, 0x60, 0x60, 0x01, 0x01) - IO (Decode16, 0x64, 0x64, 0x01, 0x01) -#ifdef SIO_EC_PS2K_IRQ - SIO_EC_PS2K_IRQ -#else - IRQ (Edge, ActiveHigh, Exclusive) {1} -#endif - } - EndDependentFn () - }) } } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief40e790fdee336fd6c786e18cd01c41fa658c2c Gerrit-Change-Number: 63521 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp/t620: Add new board HP T620
by Damien Zammit (Code Review) 10 Apr '22

10 Apr '22

Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63520 ) Change subject: mb/hp/t620: Add new board HP T620 ...................................................................... mb/hp/t620: Add new board HP T620 This is the diff applied to the previous commit to change the biostar/a68n_5200 port into support for new board: HP T620 thin client. This work was done during a coreboot hacking party! Board is AMD Fam16kb with laptop ram. coreboot console works over serial COMA by default. Board is fanless, so no need for fan control. TESTED: Boots SeaBIOS and to debian, NIC works, serial works. Missing: - Audio verb table (deleted) - PIRQs could be wrong (copied from other board) - ACPI could be wrong (copied from other board) - GPIOs (?) Caveat: Without VGA BIOS rom there are no displays. VGA ROM was extracted from /dev/mem @ 0xC0000 on a running system. Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- M src/mainboard/hp/t620/BiosCallOuts.c M src/mainboard/hp/t620/Kconfig M src/mainboard/hp/t620/Kconfig.name M src/mainboard/hp/t620/board_info.txt M src/mainboard/hp/t620/bootblock.c M src/mainboard/hp/t620/devicetree.cb 6 files changed, 40 insertions(+), 210 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/63520/1 diff --git a/src/mainboard/hp/t620/BiosCallOuts.c b/src/mainboard/hp/t620/BiosCallOuts.c index f1560c4..a0ac3f0 100644 --- a/src/mainboard/hp/t620/BiosCallOuts.c +++ b/src/mainboard/hp/t620/BiosCallOuts.c @@ -5,8 +5,6 @@ #include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> -#include "imc.h" - const BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_DO_RESET, agesa_Reset }, @@ -24,20 +22,6 @@ * AMD Olivehill Platform ALC272 Verb Table */ static const CODEC_ENTRY Olivehill_Alc272_VerbTbl[] = { - {0x11, 0x411111F0}, // - SPDIF_OUT2 - {0x12, 0x411111F0}, // - DMIC_1/2 - {0x13, 0x411111F0}, // - DMIC_3/4 - {0x14, 0x411111F0}, // Port D - LOUT1 - {0x15, 0x411111F0}, // Port A - LOUT2 - {0x16, 0x411111F0}, // - {0x17, 0x411111F0}, // Port H - MONO - {0x18, 0x01a19840}, // Port B - MIC1 - {0x19, 0x411111F0}, // Port F - MIC2 - {0x1a, 0x01813030}, // Port C - LINE1 - {0x1b, 0x411111F0}, // Port E - LINE2 - {0x1d, 0x40130605}, // - PCBEEP - {0x1e, 0x01441120}, // - SPDIF_OUT1 - {0x21, 0x01214010}, // Port I - HPOUT {0xff, 0xffffffff} }; @@ -47,113 +31,6 @@ {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} }; -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperature via I2C, - * if other software switches the I2C switch by mistake or intention. - * We recommend using IMC to control Fans, instead of HWM. - */ -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - /* Enable IMC fan control, the recommended way */ - if (CONFIG(HUDSON_IMC_FWM)) { - imc_reg_init(); - - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x4e;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x04; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x9a; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x01; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01; /* PWM stepping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */ - - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, - * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. - * So we remove it from AGESA code. Please See FchInitLateHwm. - */ - } else { - /* HWM fan control, the way not recommended */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - } -} - void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { FchParams_reset->Mode = FCH_SPI_MODE_NORMAL; @@ -164,7 +41,4 @@ { /* Azalia Controller OEM Codec Table Pointer */ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&OlivehillCodecTableList[0]); - - /* Fan Control */ - oem_fan_control(FchParams_env); } diff --git a/src/mainboard/hp/t620/Kconfig b/src/mainboard/hp/t620/Kconfig index 256121c..f897bab 100644 --- a/src/mainboard/hp/t620/Kconfig +++ b/src/mainboard/hp/t620/Kconfig @@ -1,24 +1,22 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_BIOSTAR_A68N5200_CLONE +if BOARD_HP_T620 config BOARD_SPECIFIC_OPTIONS def_bool y select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_ITE_IT8728F + select SUPERIO_ASPEED_AST2400 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_8192 select GFXUMA config MAINBOARD_DIR default "hp/t620" config MAINBOARD_PART_NUMBER - default "A68N5200" + default "T620" config HW_MEM_HOLE_SIZEK hex @@ -40,4 +38,4 @@ bool default n -endif +endif # BOARD_HP_T620 diff --git a/src/mainboard/hp/t620/Kconfig.name b/src/mainboard/hp/t620/Kconfig.name index e893341..fd55b76 100644 --- a/src/mainboard/hp/t620/Kconfig.name +++ b/src/mainboard/hp/t620/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_BIOSTAR_A68N5200_CLONE - bool "A68N-5200-CLONE" +config BOARD_HP_T620 + bool "T620" diff --git a/src/mainboard/hp/t620/board_info.txt b/src/mainboard/hp/t620/board_info.txt index b351b8e..4132ada 100644 --- a/src/mainboard/hp/t620/board_info.txt +++ b/src/mainboard/hp/t620/board_info.txt @@ -1 +1,2 @@ Category: eval +Socketed Flash: Y diff --git a/src/mainboard/hp/t620/bootblock.c b/src/mainboard/hp/t620/bootblock.c index 70bc10c..5226f4a 100644 --- a/src/mainboard/hp/t620/bootblock.c +++ b/src/mainboard/hp/t620/bootblock.c @@ -4,27 +4,10 @@ #include <bootblock_common.h> #include <stdint.h> #include <device/pci_ops.h> -#include <superio/ite/common/ite.h> -#include <superio/ite/it8728f/it8728f.h> +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> -#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) -#define CLKIN_DEV PNP_DEV(0x2e, IT8728F_GPIO) - -static void sbxxx_enable_48mhzout(void) -{ - u32 reg32; - - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ - reg32 = misc_read32(0x28); - reg32 &= 0xfff8ffff; - misc_write32(0x28, reg32); - - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ - reg32 = misc_read32(0x40); - reg32 &= 0xffffbffb; - misc_write32(0x40, reg32); -} +#define SERIAL_DEV PNP_DEV(0x2e, AST2400_SUART2) void bootblock_mainboard_early_init(void) { @@ -35,7 +18,7 @@ /* Set LPC decode enables. */ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); + pci_write_config32(dev, 0x44, 0xff03ffc0); /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); @@ -47,11 +30,6 @@ byte |= (1 << 6); /* 0x3f8 */ pci_write_config8(dev, 0x44, byte); - /* enable SIO clock */ - sbxxx_enable_48mhzout(); - - /* Enable serial output on it8728f */ - ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); - ite_kill_watchdog(GPIO_DEV); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* Enable serial output */ + aspeed_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/hp/t620/devicetree.cb b/src/mainboard/hp/t620/devicetree.cb index c036b65..ed6fa58 100644 --- a/src/mainboard/hp/t620/devicetree.cb +++ b/src/mainboard/hp/t620/devicetree.cb @@ -8,15 +8,15 @@ end device domain 0 on - subsystemid 0x1022 0x1410 inherit + subsystemid 0x103c 0x2187 inherit chip northbridge/amd/agesa/family16kb device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia + device pci 1.0 on end # Internal Graphics + device pci 1.1 on end # Internal HDMI Audio device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 off end # mPCIe slot - device pci 2.3 off end # Realtek NIC + device pci 2.1 off end + device pci 2.2 on end + device pci 2.3 on end device pci 2.4 off end # Edge Connector device pci 2.5 off end # Edge Connector end #chip northbridge/amd/agesa/family16kb @@ -28,42 +28,23 @@ device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - #register "multi_function_register_1" = "0x01" - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + device pci 14.0 on end # SMBus + device pci 14.2 on end # Audio Azalia + device pci 14.3 on # LPC + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + register "use_espi" = "0" + device pnp 2e.2 off end # SUART1 + device pnp 2e.3 on # SUART2 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0x71 = 3 + irq 0xf0 = 2 + end + end end - device pnp 2e.2 off end # COM2 - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 5 - drq 0x74 = 4 - end - device pnp 2e.4 on # Hardware Monitor - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - irq 0xf1 = 0x00 - irq 0xf2 = 0x04 - irq 0xf3 = 0xa0 - irq 0xf5 = 0x0f - irq 0xf9 = 0xa0 - irq 0xfa = 0x04 - end - device pnp 2e.5 on # KBC - io 0x60 = 0x60 - end - device pnp 2e.6 off end # KBC? - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end - device pnp 2e.9 off end - device pnp 2e.a off end # IR - end # ITE IT8728F + end end #LPC device pci 14.7 off end # SD end #chip southbridge/amd/agesa/hudson @@ -75,12 +56,10 @@ device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + register "spdAddrLookup" = "{ + { {0xA0, 0xA2}, {0x00, 0x00}, }, + { {0x00, 0x00}, {0x00, 0x00}, }, }" end - - end #domain + end end #northbridge/amd/agesa/family16kb/root_complex -- To view, visit https://review.coreboot.org/c/coreboot/+/63520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaa724f393194f762d55263a74b04c9fde93e53f Gerrit-Change-Number: 63520 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-MessageType: newchange

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