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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS4:
> Right now the only mechanism for custom code in the SMI sleep path is `mainboard_smi_sleep()`, alth […]
My concern I guess would be adding a new weak SoC smihandler_sleep function(), when this should hopefully be reverted soon-ish, and then it is no longer needed.
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Change subject: drivers/usb/pci_xhci: Add Sabrina xhci pci device id
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/usb/pci_xhci/pci_xhci.c:
https://review.coreboot.org/c/coreboot/+/63641/comment/8553955f_db96f34b
PS1, Line 262: PCI_DID_AMD_FAM17H_MODELA0H_XHCI2
> ouch, missed this one when creating the sabrina soc code
@Raul, I will look into it once all the peripherals are verified and upload a follow-up patch.
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Change subject: mb/google/brya: Create osiris variant
......................................................................
Patch Set 1: Code-Review+2
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Change subject: drivers/usb/pci_xhci: Add Sabrina xhci pci device id
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63641/comment/5999b681_062da455
PS1, Line 7: devce
> device
Done
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Hello build bot (Jenkins), Raul Rangel, Jon Murphy, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63641
to look at the new patch set (#2).
Change subject: drivers/usb/pci_xhci: Add Sabrina xhci pci device id
......................................................................
drivers/usb/pci_xhci: Add Sabrina xhci pci device id
BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that the XHCI controllers
are enumerated successfully and ACPI device objects are added in SSDT.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: I7ad4555212ed38ea0f9029275345e4945855a8c3
---
M src/drivers/usb/pci_xhci/pci_xhci.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63641/2
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Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/alderlake/chipset_pch_s.cb:
https://review.coreboot.org/c/coreboot/+/63493/comment/41a0a415_649fe544
PS8, Line 84: 2.10
This is hex, should be 2.a
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Change subject: [WIP] mb/google,intel: Split chromeos.c files
......................................................................
Abandoned
We could solve this my rethinking some of the headers used.
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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
Patch Set 6:
(1 comment)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/44634d33_0a2a0c24
PS6, Line 27: static unsigned int fx_devs = 0;
> Agreed, but it seems like a change for a separate follow-up patch
Considering parameters passed to moved copy of dram_base_limit() this would have been better done first. I don't mind if you mark this resolved but I would like to have that follow-up appear for review too.
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Change subject: nb/amd/common: Move RAM calcualtion to common code
......................................................................
Patch Set 6:
(1 comment)
File src/northbridge/amd/agesa/family14/northbridge.c:
https://review.coreboot.org/c/coreboot/+/61682/comment/9ca049ba_df117886
PS6, Line 27: static unsigned int fx_devs = 0;
> These arrays reduce to single struct device *, therefore any loops with FX_DEVS or fx_devs or nodeid […]
Agreed, but it seems like a change for a separate follow-up patch
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