coreboot-gerrit April 2022

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Change in coreboot[master]: libpayload/pci: Add pci_map_bus function for MediaTek platform
by Jianjun Wang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Arthur Heymans, Jianjun Wang. Hello build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56794 to look at the new patch set (#67). Change subject: libpayload/pci: Add pci_map_bus function for MediaTek platform ...................................................................... libpayload/pci: Add pci_map_bus function for MediaTek platform Add 'pci_map_bus' function and PCIE_MEDIATEK config for MediaTek platform. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pcie_mediatek.c 3 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/67 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 67 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/pci: Add support for bus mapping
by Jianjun Wang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Hung-Te Lin, Furquan Shaikh, Angel Pons, Arthur Heymans, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56789 to look at the new patch set (#65). Change subject: libpayload/pci: Add support for bus mapping ...................................................................... libpayload/pci: Add support for bus mapping Move the common APIs to pci_ops.c and IO based operations to pci_io_ops.c, and add pci_map_bus_ops.c to support bus mapping. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pci_io_ops.c A payloads/libpayload/drivers/pci_map_bus_ops.c R payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/pci.h 6 files changed, 138 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56789/65 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 65 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Fill coreboot table with PCIe info
by Jianjun Wang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63252 to look at the new patch set (#19). Change subject: soc/mediatek: Fill coreboot table with PCIe info ...................................................................... soc/mediatek: Fill coreboot table with PCIe info In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 --- M src/soc/mediatek/common/pcie.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63252/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/63252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Gerrit-Change-Number: 63252 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63251 to look at the new patch set (#18). Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... coreboot_tables: Add PCIe info to coreboot table Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/bsd/include/commonlib/bsd/cb_err.h M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 7 files changed, 51 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63251/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
by Teddy Shih (Code Review) 15 Apr '22

15 Apr '22

Teddy Shih has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63652 ) Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR ...................................................................... mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR To meet LTE's RF Specific Absorption Rate (SAR) certification, we add a Semtech Smart Proximity Sensor (P-Sensor) SX9324 for SAR. P-Sensor connects EC of I2C 5 bus and GPIO D22, D23, as well as, SoC of GPIO E11, according to mainboard schematic. BUG=b:213549229 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Change-Id: If172d13aa62503547227adf91f049ea50b948888 --- M src/mainboard/google/dedede/variants/beadrix/gpio.c M src/mainboard/google/dedede/variants/beadrix/overridetree.cb 2 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63652/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/gpio.c b/src/mainboard/google/dedede/variants/beadrix/gpio.c index 57573cc..764df2e 100644 --- a/src/mainboard/google/dedede/variants/beadrix/gpio.c +++ b/src/mainboard/google/dedede/variants/beadrix/gpio.c @@ -38,6 +38,10 @@ PAD_NC(GPP_D20, NONE), /* D21 : WWAN_WLAN_COEX3 ==> TP */ PAD_NC(GPP_D21, NONE), + /* D22 : AP_I2C_SUB_SDA*/ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), + /* D23 : AP_I2C_SUB_SCL */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* E1 : EMR_RESET_L ==> NC */ PAD_NC(GPP_E1, NONE), @@ -47,6 +51,8 @@ PAD_NC(GPP_E5, NONE), /* E10 : GPP_E10/SML_DATA0 ==> NC */ PAD_NC(GPP_E10, NONE), + /* E11 : AP_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E11, NONE, PLTRST, LEVEL, NONE), /* G0 : SD_CMD ==> NC */ PAD_NC(GPP_G0, NONE), diff --git a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb index 8a12e41..43039bc 100644 --- a/src/mainboard/google/dedede/variants/beadrix/overridetree.cb +++ b/src/mainboard/google/dedede/variants/beadrix/overridetree.cb @@ -18,6 +18,7 @@ #| I2C2 | Touchscreen | #| I2C3 | Camera | #| I2C4 | Audio | + #| I2C5 | P-sensor(LTE) | #+-------------------+---------------------------+ register "common_soc_config" = "{ .gspi[0] = { @@ -39,6 +40,9 @@ .i2c[4] = { .speed = I2C_SPEED_FAST, }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, }" device domain 0 on @@ -131,6 +135,61 @@ device i2c 1a on end end end # I2C 4 + device pci 19.1 on + chip drivers/i2c/sx9324 + register "hid" = ""STH9324"" + register "name" = ""SEMTECH SX9324"" + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E11_IRQ)" + register "reg_gnrl_ctrl0" = "0x0a" + register "reg_gnrl_ctrl1" = "0x22" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x01" + register "reg_afe_ctrl4" = "0x47" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x47" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x0f" + register "reg_afe_ph0" = "0x37" + register "reg_afe_ph1" = "0x29" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x2d" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x40" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x6f" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + device i2c 28 on end + end + end # I2C 5 device pci 1c.6 off end # PCI Express Root Port 7 / SATA_0. Baseboard/devicetree.cb is off device pci 1c.7 off end # PCI Express Root Port 8 / SATA_1 device pci 1f.3 on -- To view, visit https://review.coreboot.org/c/coreboot/+/63652 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If172d13aa62503547227adf91f049ea50b948888 Gerrit-Change-Number: 63652 Gerrit-PatchSet: 1 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... Patch Set 17: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/cb_err.h: https://review.coreboot.org/c/coreboot/+/63251/comment/0f5b8ab7_568ba468 PS16, Line 18: > Add one tab for alignment. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 17 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 09:39:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Rex-BC Chen, Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63251 to look at the new patch set (#17). Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... coreboot_tables: Add PCIe info to coreboot table Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 --- M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/bsd/include/commonlib/bsd/cb_err.h M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 7 files changed, 51 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63251/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 17 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Create osiris variant
by David Wu (Code Review) 15 Apr '22

15 Apr '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63650 ) Change subject: mb/google/brya: Create osiris variant ...................................................................... mb/google/brya: Create osiris variant Create the osiris variant of the brya0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:229352299 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_OSIRIS Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I41e088a3415add86cba87c919af23494f816bb24 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/osiris/include/variant/ec.h A src/mainboard/google/brya/variants/osiris/include/variant/gpio.h A src/mainboard/google/brya/variants/osiris/memory/Makefile.inc A src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/osiris/overridetree.cb 8 files changed, 46 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/63650/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 0fafc2f..a1286c3 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -119,6 +119,7 @@ default 0x1 if BOARD_GOOGLE_BANSHEE default 0x1 if BOARD_GOOGLE_KINOX default 0x0 if BOARD_GOOGLE_CRAASK + default 0x1 if BOARD_GOOGLE_OSIRIS config DRIVER_TPM_I2C_ADDR hex @@ -172,6 +173,7 @@ default "Moli" if BOARD_GOOGLE_MOLI default "Kinox" if BOARD_GOOGLE_KINOX default "Craask" if BOARD_GOOGLE_CRAASK + default "Osiris" if BOARD_GOOGLE_OSIRIS config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -200,6 +202,7 @@ default "moli" if BOARD_GOOGLE_MOLI default "kinox" if BOARD_GOOGLE_KINOX default "craask" if BOARD_GOOGLE_CRAASK + default "osiris" if BOARD_GOOGLE_OSIRIS config VBOOT select VBOOT_EARLY_EC_SYNC diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b79fce6..2f81da0a 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -196,3 +196,7 @@ config BOARD_GOOGLE_CRAASK bool "-> Craask" select BOARD_GOOGLE_BASEBOARD_NISSA + +config BOARD_GOOGLE_OSIRIS + bool "-> Osiris" + select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/osiris/include/variant/ec.h b/src/mainboard/google/brya/variants/osiris/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/osiris/include/variant/gpio.h b/src/mainboard/google/brya/variants/osiris/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/memory/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt new file mode 100644 index 0000000..9621137 --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/osiris/overridetree.cb b/src/mainboard/google/brya/variants/osiris/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/osiris/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/63650 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e088a3415add86cba87c919af23494f816bb24 Gerrit-Change-Number: 63650 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush: Enable tablet mode switch
by Kenneth Chan (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Hello Bhanu Prakash Maiya, Rob Barnes, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63649 to look at the new patch set (#3). Change subject: mb/google/guybrush: Enable tablet mode switch ...................................................................... mb/google/guybrush: Enable tablet mode switch Enable tablet mode switch to fix can't switch to tablet mode issue. BUG=b:228868883 BRANCH=guybrush TEST=local build test on Dewatt: testing tablet mode switch Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/63649/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Gerrit-Change-Number: 63649 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/guybrush: Enable tablet mode switch
by Kenneth Chan (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63649 ) Change subject: mb/google/guybrush: Enable tablet mode switch ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Gerrit-Change-Number: 63649 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:56:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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