coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/81f14cb4_99cdbf89 PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms > > Enabling MCHBAR takes a PCI config register write or two, so size isn't a concern. The main reason is that the GPMR driver needs to access MCHBAR registers in bootblock code. > > +1 to Angel's question. do we need to use GPMR access even in bootblock. Today with ADL and previous generation I don't see such usage. Well, only MTL needs MCHBAR access to configure GPMR stuff, the registers are in DMI PCR space for older platforms. AFAIUI, the GPMR driver is needed to configure some decode ranges in bootblock, I think stuff like ACPIBASE, PMBASE, SMBUS TCOBASE, LPC I/O enable/decode, etc. could need the GPMR driver in bootblock. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:57:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration
by Subrata Banik (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Christian Walter, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63631 ) Change subject: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63631/comment/3eb77d1a_39f1e814 PS3, Line 10: has implemented > implements Ack https://review.coreboot.org/c/coreboot/+/63631/comment/aa3c2399_6ebddef3 PS3, Line 9: as now IA : common code lockdown.c has implemented the lpc registers lock down : configuration as well > Maybe mention the commit doing that. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 Gerrit-Change-Number: 63631 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:47:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration
by Subrata Banik (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Subrata Banik, Jonathan Zhang, Matt DeVillier, Tim Wawrzynczak, Christian Walter, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Tim Chu. Hello build bot (Jenkins), Jonathan Zhang, Matt DeVillier, Paul Menzel, Angel Pons, Arthur Heymans, Eric Lai, Marc Jones, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Christian Walter, Nick Vaccaro, Lean Sheng Tan, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63631 to look at the new patch set (#4). Change subject: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration ...................................................................... soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration This patch drops SoC specific lpc lock down configuration as commit 63630 (soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration) implements the lpc registers lock down configuration in common code. BUG=b:211954778 TEST=Build. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 --- M src/soc/intel/skylake/lockdown.c M src/soc/intel/xeon_sp/lockdown.c 2 files changed, 0 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/63631/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 Gerrit-Change-Number: 63631 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Paul Menzel, Angel Pons. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/63615/comment/f17ac614_3b14417d PS4, Line 61: sa_set_pci_bar(soc_fixed_pci_resources, : ARRAY_SIZE(soc_fixed_pci_resources)); > can you directly perform the PCI write to set the MCH BAR? you might don't need those resource array […] +1. Something like this: pci_write_config32(SA_DEV_ROOT, MCHBAR + 4, 0); pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); The order shouldn't matter, but I've chosen to write the low DWORD last because it's when the enable bit is set. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:45:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Subrata Banik (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Wonkyu Kim, Paul Menzel, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/25af1ba3_8fbba25b PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms > Enabling MCHBAR takes a PCI config register write or two, so size isn't a concern. The main reason is that the GPMR driver needs to access MCHBAR registers in bootblock code. +1 to Angel's question. do we need to use GPMR access even in bootblock. Today with ADL and previous generation I don't see such usage. https://review.coreboot.org/c/coreboot/+/63615/comment/7d4ea582_2b015909 PS4, Line 13: > Yes, I'd consider removing the code enabling MCHBAR in romstage. Yes, if we need this is call in bootblock then better to remove from romstage -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:45:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Wonkyu Kim, Paul Menzel. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/0bb5f591_d20ea341 PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms > So the benefit is code unification? To my understanding the bootblock really should be as small as p […] Enabling MCHBAR takes a PCI config register write or two, so size isn't a concern. The main reason is that the GPMR driver needs to access MCHBAR registers in bootblock code. https://review.coreboot.org/c/coreboot/+/63615/comment/1590673a_5b2429a2 PS4, Line 13: > Don’t you need to remove also code from the other platforms doing this in romstage? Yes, I'd consider removing the code enabling MCHBAR in romstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:43:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0
by Paul Menzel (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Arthur Heymans, Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63123 ) Change subject: crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0 ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: It’d be great to get this updated, and committed. -- To view, visit https://review.coreboot.org/c/coreboot/+/63123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a Gerrit-Change-Number: 63123 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:40:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [only for test] test gcc-12 snapshot
by Paul Menzel (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61533 ) Change subject: [only for test] test gcc-12 snapshot ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Some changes to address unwanted warnings were added to GCC 12 development, so it’d be great if you could respin this for build testing. -- To view, visit https://review.coreboot.org/c/coreboot/+/61533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2545f4119a20eec6482fbdf8993eb842af96a0a7 Gerrit-Change-Number: 61533 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:39:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration
by Paul Menzel (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Subrata Banik, Jonathan Zhang, Matt DeVillier, Tim Wawrzynczak, Christian Walter, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63631 ) Change subject: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63631/comment/5a2db0ee_d6e1b415 PS3, Line 10: has implemented implements https://review.coreboot.org/c/coreboot/+/63631/comment/0df5e9b1_2053cc24 PS3, Line 9: as now IA : common code lockdown.c has implemented the lpc registers lock down : configuration as well Maybe mention the commit doing that. -- To view, visit https://review.coreboot.org/c/coreboot/+/63631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2 Gerrit-Change-Number: 63631 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:28:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/baseboard/brask: fix boot beep
by Dtrain Hsu (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Felix Held. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63645 ) Change subject: mb/google/brya/variants/baseboard/brask: fix boot beep ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63645/comment/33f6d8f4_af29de2a PS1, Line 8: > Please start by describing the problem. […] Thanks for review. https://review.coreboot.org/c/coreboot/+/63645/comment/d157b979_456e1632 PS1, Line 9: GPP_B14 is used for PWM_PP3300_BUZZER. : The gpio lock causes boot beep fail. : Modify GPP_B4 from PAD_CFG_NF_LOCK to PAD_CFG_NF. > Please reflow for 72 characters per line. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Gerrit-Change-Number: 63645 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 07:27:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022