coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/guybrush: Enable tablet mode switch
by Kenneth Chan (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Rob Barnes. Hello Bhanu Prakash Maiya, Rob Barnes, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63649 to look at the new patch set (#2). Change subject: mb/google/guybrush: Enable tablet mode switch ...................................................................... mb/google/guybrush: Enable tablet mode switch Enable tablet mode switch to fix dewatt can't switch to tablet mode. BUG=b:228868883 BRANCH=guybrush TEST=local build test on Dewatt: testing tablet mode switch Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/63649/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Gerrit-Change-Number: 63649 Gerrit-PatchSet: 2 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush: Enable tablet mode switch
by Kenneth Chan (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Bhanu Prakash Maiya, Rob Barnes. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63649 ) Change subject: mb/google/guybrush: Enable tablet mode switch ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Gerrit-Change-Number: 63649 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:53:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable tablet mode switch
by Kenneth Chan (Code Review) 15 Apr '22

15 Apr '22

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63649 ) Change subject: mb/google/guybrush: Enable tablet mode switch ...................................................................... mb/google/guybrush: Enable tablet mode switch Enable tablet mode switch back. BUG=b:228868883 BRANCH=guybrush TEST=local build test on Dewatt: testing tablet mode switch Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/63649/1 diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h index 5695a8e..d516b95 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h @@ -61,6 +61,9 @@ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GEVENT_3 /* AGPIO 22 -> GPE 3 */ +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + #define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Gerrit-Change-Number: 63649 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: option: Allow to use the EFI variable driver as option backend
by Patrick Rudolph (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Sean Rhodes, Michał Żygowski, Matt DeVillier, Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62562 ) Change subject: option: Allow to use the EFI variable driver as option backend ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62562/comment/4e553f54_e800626c PS3, Line 9: region > nit: move to next line to honor the 72 character limit Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I520eca96bcd573f825ed35a29bf8f750e313a02d Gerrit-Change-Number: 62562 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:46:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card
by Chen Wisley (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63648 to review the following change. Change subject: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card ...................................................................... mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card Configure the power saving pin for Smart Card. BUG=b:229356121 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/anahera/gpio.c M src/mainboard/google/brya/variants/anahera4es/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63648/1 diff --git a/src/mainboard/google/brya/variants/anahera/gpio.c b/src/mainboard/google/brya/variants/anahera/gpio.c index 9483d56..02ebeb8 100644 --- a/src/mainboard/google/brya/variants/anahera/gpio.c +++ b/src/mainboard/google/brya/variants/anahera/gpio.c @@ -61,6 +61,8 @@ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E22 : DDPA_CTRLCLK ==> SC_PWR_SV */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), diff --git a/src/mainboard/google/brya/variants/anahera4es/gpio.c b/src/mainboard/google/brya/variants/anahera4es/gpio.c index 132dbf6..12f73fc 100644 --- a/src/mainboard/google/brya/variants/anahera4es/gpio.c +++ b/src/mainboard/google/brya/variants/anahera4es/gpio.c @@ -65,6 +65,8 @@ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E20 : USB_C1_LSX_SOC_TX ==> EN_PP3300_eMMC */ PAD_CFG_GPO(GPP_E20, 1, DEEP), + /* E22 : DDPA_CTRLCLK ==> SC_PWR_SV */ + PAD_CFG_GPO(GPP_E22, 1, DEEP), /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/63648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Gerrit-Change-Number: 63648 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/update_microcode: Make ucode update more generic
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63589 ) Change subject: soc/amd/common/block/update_microcode: Make ucode update more generic ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Why doesn't the microcode header have a size field? -- To view, visit https://review.coreboot.org/c/coreboot/+/63589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Gerrit-Change-Number: 63589 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:30:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Felix Singer, Jason Glenesk, Raul Rangel, Nico Huber, Furquan Shaikh, Marshall Dawson, Tim Wawrzynczak, Michael Niewöhner, Patrick Rudolph, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58118 ) Change subject: acpigen,soc/amd/cezanne,intel/{common,skl}: rework CPPC table passing ...................................................................... Patch Set 9: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/58118/comment/8d469c49_7f5e3d26 PS9, Line 12: Test: dumped SSDT before and after do not differ. On which machine? File src/cpu/intel/common/common_init.c: https://review.coreboot.org/c/coreboot/+/58118/comment/5924fb85_9c3504d3 PS9, Line 134: *version = CPPC_VERSION_2; I'd use `CPPC_VERSION_3` here. Context: The code in soc/intel was changed and the CPPC version now depends on `SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID`. As the Kconfig option is specific to soc/intel, I'd return the highest supported CPPC version here, and lower it in soc/intel according to the Kconfig option. File src/soc/amd/cezanne/cppc.c: https://review.coreboot.org/c/coreboot/+/58118/comment/fc810e97_e292df36 PS9, Line 42: const cppc_entry_t *cpu_get_cppc_table(u32 *version, u32 *size) Do you need this function to be public? It's not used outside of this file. In fact, I'd get rid of it and call `acpigen_write_CPPC_package()` directly with the right parameters. File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/58118/comment/92ce0517_0b19d49a PS9, Line 387: acpigen_write_CPPC_package(cppc_table, version, size); This has changed, now the CPPC version can be 2 or 3 depending on the `SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID` Kconfig option. I would have `cpu_get_cppc_table()` return CPPC_VERSION_3 (the highest supported CPPC version) and change the value to CPPC_VERSION_2 if the `SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID` option is not enabled. I'm thinking of something like this: if (core_id == 0) { u32 version, size; const cppc_entry_t *cppc_table = cpu_get_cppc_table(&version, &size); if (!CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID)) version = CPPC_VERSION_2; acpigen_write_CPPC_package(cppc_table, version, size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/58118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26c5e80c2a16a50ed73245c7c32d61b17e45c22a Gerrit-Change-Number: 58118 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:24:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/z220_series: Add Z220 CMT Workstation variant
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Damien Zammit. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62809 ) Change subject: mb/hp/z220_series: Add Z220 CMT Workstation variant ...................................................................... Patch Set 8: Code-Review+2 (1 comment) File src/mainboard/hp/z220_series/variants/z220_cmt_workstation/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62809/comment/897bbb01_5f6422c1 PS3, Line 5: subsystemid 0x103c 0x1791 inherit > No, I think without this line, the whole southbridge has the wrong subsystemid because the missing l […] Hmmm, you can look at the generated static.c to see what happens. -- To view, visit https://review.coreboot.org/c/coreboot/+/62809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Gerrit-Change-Number: 62809 Gerrit-PatchSet: 8 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Comment-Date: Fri, 15 Apr 2022 08:10:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Damien Zammit Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/{block, pch}: Migrate GPMR driver
by Angel Pons (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Wonkyu Kim, Ravishankar Sarawadi, Nick Vaccaro, Tim Wawrzynczak. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63471 ) Change subject: soc/intel/cmn/{block, pch}: Migrate GPMR driver ...................................................................... Patch Set 13: (3 comments) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/63471/comment/9bec7bb5_32afd57d PS13, Line 29: gpmr_write32 This write was changed from 16 bits to 32 bits, is it OK? https://review.coreboot.org/c/coreboot/+/63471/comment/81258ea1_192f8096 PS13, Line 47: gpmr_write32 Ditto. File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63471/comment/5c124065_cc07d821 PS13, Line 40: gpmr_or32(GPMR_GCS, GPMR_GCS_BILD); : : /* : * Set Secure Register Lock (SRL) bit in DMI control register to lock : * DMI configuration. : */ : gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); Does MTL have these registers in MCHBAR? -- To view, visit https://review.coreboot.org/c/coreboot/+/63471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Gerrit-Change-Number: 63471 Gerrit-PatchSet: 13 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:04:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Subrata Banik (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Wonkyu Kim, Paul Menzel, Angel Pons. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/e5ddcdca_b9f9adaa PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms > > > Enabling MCHBAR takes a PCI config register write or two, so size isn't a concern. The main reason is that the GPMR driver needs to access MCHBAR registers in bootblock code. > > > > +1 to Angel's question. do we need to use GPMR access even in bootblock. Today with ADL and previous generation I don't see such usage. > > Well, only MTL needs MCHBAR access to configure GPMR stuff, the registers are in DMI PCR space for older platforms. AFAIUI, the GPMR driver is needed to configure some decode ranges in bootblock, I think stuff like ACPIBASE, PMBASE, SMBUS TCOBASE, LPC I/O enable/decode, etc. could need the GPMR driver in bootblock. There are two PMC IP, so I believe you are right, to configure PMC controller for IOC die, we need additional IOC driver. Like to hear the new flow from Will in more details. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 08:00:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022