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Change subject: soc/intel/alderlake: Enable Pre Reset CPU Telemetry
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63616/comment/2a0ebfc1_0dda4f4d
PS2, Line 11: TEST=Boot to OS
On what device?
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Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63630/comment/dbb8c636_ab40880b
PS3, Line 103: lpc_set_eiss
> This should do the same as fast_spi_lockdown_cfg(). I think that lpc_enable_wp() needs to be added to match.
make sense to me as I could see the same register snapshot there for eSPI/LPC as well.
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Change subject: test/lib: Add non-existent DIMMs test case in spd_cache-test
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Patch Set 1: Code-Review+1
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Change subject: amdfwtool: Change the name of macros for 'BHD'
......................................................................
Patch Set 27:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55411/comment/2cc47d8b_c2742128
PS27, Line 9: Use BHD instead of BDT as the name of cookie macro.
: Use L2 to make it clear it is for level 2. The 'BHD2' is misleading,
: which is going to be used for combo entry.
: The definition in psp_verstage is also changed.
Please mark it up as a list, or do not wrap lines just because a sentence ends.
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Change subject: Documentation: Add Dasharo to after-market firmware list
......................................................................
Patch Set 4:
(1 comment)
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/63396/comment/79df7a41_c7d860ba
PS4, Line 60: open source
I think in [1], “open-source based” was suggested.
[1]: https://review.coreboot.org/c/homepage/+/63402
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Change subject: Documentation: Add NovaCustom laptops to ships-with-coreboot hw list
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Patch Set 2: Code-Review+1
(1 comment)
File Documentation/distributions.md:
https://review.coreboot.org/c/coreboot/+/63389/comment/7fd8d55e_72cbc079
PS2, Line 15: Windows
Microsoft Windows
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Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63615/comment/41e0cd5f_fe1ced2e
PS4, Line 9: Meteorlake
Meteor Lake
https://review.coreboot.org/c/coreboot/+/63615/comment/ab7fcd53_6a3a2f01
PS4, Line 11: enabling
enable
https://review.coreboot.org/c/coreboot/+/63615/comment/c54440ea_4df5c464
PS4, Line 10: As there is no harm to enable
: MCHBAR from bootblock even in existing plaforms
So the benefit is code unification? To my understanding the bootblock really should be as small as possible, so probably more advantages should be mentioned.
https://review.coreboot.org/c/coreboot/+/63615/comment/1c949c21_b6e65e7a
PS4, Line 13:
Don’t you need to remove also code from the other platforms doing this in romstage?
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Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/systemagent/systemagent_early.c:
https://review.coreboot.org/c/coreboot/+/63615/comment/52006c4f_fcfef1a5
PS4, Line 61: sa_set_pci_bar(soc_fixed_pci_resources,
: ARRAY_SIZE(soc_fixed_pci_resources));
can you directly perform the PCI write to set the MCH BAR? you might don't need those resource array.
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Change subject: soc/intel/common: Implement IOC driver
......................................................................
Patch Set 17:
(3 comments)
File src/soc/intel/common/block/ioc/ioc.c:
https://review.coreboot.org/c/coreboot/+/63198/comment/38ef7848_1a61e123
PS17, Line 12: get_mchbar
I would have written this logic as below
1. Read and check if MCH BAR is already assigned and Enable bit is set. Then return MCHBAR
2. Else, call below function to set the MCH BAR and return the same.
sa_set_mch_bar(soc_fixed_mch_resources,
ARRAY_SIZE(soc_fixed_mch_resources));
In either case, I would have move this into systemagent_early.c file as well.
https://review.coreboot.org/c/coreboot/+/63198/comment/f0379457_8d848a40
PS17, Line 16: if(
if (
https://review.coreboot.org/c/coreboot/+/63198/comment/1373b143_f75692ce
PS17, Line 25: void ioc_reg_write32(uint32_t offset, uint32_t value)
: {
: uint32_t mchbar = get_mchbar();
:
: if(mchbar)
: write32p(MCH_BASE_ADDRESS + offset, value);
: }
void ioc_reg_write32(uint32_t offset, uint32_t value)
{
uint32_t mchbar = get_mchbar();
write32p(mchbar + offset, value);
}
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