coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: mb/hp/z220_series: Add Z220 CMT Workstation variant
by Edward O'Callaghan (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Damien Zammit. Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62809 ) Change subject: mb/hp/z220_series: Add Z220 CMT Workstation variant ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b298921e6f509440ec7b049e086c0878f708bd3 Gerrit-Change-Number: 62809 Gerrit-PatchSet: 8 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Damien Zammit Gerrit-Comment-Date: Fri, 15 Apr 2022 01:55:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ss
by Kevin Chiu (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Bhanu Prakash Maiya, Rob Barnes, Eric Peers, Felix Held. Hello build bot (Jenkins), Bhanu Prakash Maiya, Rob Barnes, Eric Peers, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63537 to look at the new patch set (#4). Change subject: mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ss ...................................................................... mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ss BUG=b:227296841 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass PLT criteria: S0 > 600ms, s0i3 > 14 days Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68 Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/variant.c 1 file changed, 5 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/63537/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c61e1d0f3db8b9885040255d6de266616768b68 Gerrit-Change-Number: 63537 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya: Add Kconfig for TPM I2C bus
by Raihow Shi (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63635 ) Change subject: mb/google/brya: Add Kconfig for TPM I2C bus ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63635/comment/85c0ab1e_270613fb PS2, Line 7: mb/google/brya: Add TPM I2C for moli > suggestion: […] done -- To view, visit https://review.coreboot.org/c/coreboot/+/63635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Gerrit-Change-Number: 63635 Gerrit-PatchSet: 3 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 01:25:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Add Kconfig for TPM I2C bus
by Raihow Shi (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Raihow Shi, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63635 to look at the new patch set (#3). Change subject: mb/google/brya: Add Kconfig for TPM I2C bus ...................................................................... mb/google/brya: Add Kconfig for TPM I2C bus Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/63635/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Gerrit-Change-Number: 63635 Gerrit-PatchSet: 3 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: ec/google/chromeec: add fan speed rpm control
by Eric Lai (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Sumeet R Pawnikar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62789 ) Change subject: ec/google/chromeec: add fan speed rpm control ...................................................................... Patch Set 3: (1 comment) File src/ec/google/chromeec/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/62789/comment/f21e24ab_3a8c5733 PS3, Line 85: CFSP, 16, // Set Fan speed in rpm I think we need identify EC offset. This is conflict to https://review.coreboot.org/c/coreboot/+/62946/9/src/ec/google/chromeec/acp… -- To view, visit https://review.coreboot.org/c/coreboot/+/62789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb1646b1fb1659fd853ece97d97bb9dee2a3f57e Gerrit-Change-Number: 62789 Gerrit-PatchSet: 3 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 01:17:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: remove i2c1 in overridetree
by Raihow Shi (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63545 ) Change subject: mb/google/brask/variants/moli: remove i2c1 in overridetree ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63545/comment/c3cf741e_898b557f PS5, Line 7: for moli > Remove as already part of the prefix. done https://review.coreboot.org/c/coreboot/+/63545/comment/d699470f_9364076a PS5, Line 9: is already have > already has it. done https://review.coreboot.org/c/coreboot/+/63545/comment/0de32bf5_26f3ad24 PS5, Line 9: remove > Remove done -- To view, visit https://review.coreboot.org/c/coreboot/+/63545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Gerrit-Change-Number: 63545 Gerrit-PatchSet: 6 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 01:12:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: remove i2c1 in overridetree
by Raihow Shi (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: YH Lin, Zhuohao Lee, Raihow Shi, Felix Held. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63545 to look at the new patch set (#6). Change subject: mb/google/brask/variants/moli: remove i2c1 in overridetree ...................................................................... mb/google/brask/variants/moli: remove i2c1 in overridetree Remove i2c1 because brask devicetree is already has it. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/63545/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Gerrit-Change-Number: 63545 Gerrit-PatchSet: 6 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree for moli
by Ariel Fang (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: YH Lin, Subrata Banik, Tim Wawrzynczak, Paul Menzel, Eric Lai, Zhuohao Lee, Raihow Shi, Felix Held. Ariel Fang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63080 ) Change subject: mb/google/brask/variants/moli: update overridetree for moli ...................................................................... Patch Set 17: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63080/comment/61fbcaad_5aeffab2 PS7, Line 8: option STORAGE_NVME 0 : option STORAGE_EMMC 1 > Reopen this thread. I still don't get the answer in the b/220039297. […] Hi Zhuohao, To clarify - 1. Both eMMC connector and SSD connctor are always populated on MB design, we don't seperate MB by storage option. 2. The system only supports either eMMC or SSD according to MP SKU configuation. ODM will base on MP SKU config to set CBI value before shipment. 3. RMA center can't identify the repaired MB is eMMC or SSD boot. Thansk! -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 17 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 01:08:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Zhuohao Lee <zhuohao(a)google.com> Comment-In-Reply-To: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: test/lib: Add non-existent DIMMs test case in spd_cache-test
by Eric Lai (Code Review) 15 Apr '22

15 Apr '22

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63642 ) Change subject: test/lib: Add non-existent DIMMs test case in spd_cache-test ...................................................................... test/lib: Add non-existent DIMMs test case in spd_cache-test Add non-existent DIMMs test case in spd_cache-test. BUG=b:213964936 TEST=test passed Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I19b5ff7fb210b68a4ada18d8387de4ebcd054145 --- M tests/lib/spd_cache-test.c 1 file changed, 21 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/63642/1 diff --git a/tests/lib/spd_cache-test.c b/tests/lib/spd_cache-test.c index 48f06e3..c1a6113 100644 --- a/tests/lib/spd_cache-test.c +++ b/tests/lib/spd_cache-test.c @@ -11,6 +11,13 @@ struct region_device flash_rdev_rw; static char *flash_buffer = NULL; static size_t flash_buffer_size = 0; +static u8 valid_addr_map[][4] = { + {0x50, 0x51, 0x52, 0x53}, + {0x50, 0, 0x52, 0}, + {0, 0x51, 0, 0x53}, + {0x50, 0, 0, 0}, + {0, 0, 0x52, 0}, + }; static int setup_spd_cache(void **state) { @@ -38,6 +45,7 @@ free(flash_buffer); flash_buffer = NULL; flash_buffer_size = 0; + valid_addr_map = {0}; return 0; } @@ -216,18 +224,21 @@ { uint8_t *spd_cache; size_t spd_cache_sz; - struct spd_block blk = {.addr_map = {0x50, 0x51, 0x52, 0x53}, - .spd_array = {0}, .len = 0}; + struct spd_block blk = {.addr_map = {0}, .spd_array = {0}, .len = 0}; - assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); - fill_spd_cache_ddr4(spd_cache, spd_cache_sz); - assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); - get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); - *(u32 *)(spd_cache + SC_SPD_OFFSET(0) + DDR4_SPD_SN_OFF) = 0x43211234; + for (uint8_t i = 0; i < arraysize(valid_addr_map); i++) { + blk.addr_map = valid_addr_map[i]; + assert_int_equal(CB_SUCCESS, load_spd_cache(&spd_cache, &spd_cache_sz)); + fill_spd_cache_ddr4(spd_cache, spd_cache_sz); + assert_int_equal(CB_SUCCESS, spd_fill_from_cache(spd_cache, &blk)); + get_sn_from_spd_cache(spd_cache, get_spd_sn_ret_sn); + *(u32 *)(spd_cache + SC_SPD_OFFSET(0) + DDR4_SPD_SN_OFF) = 0x43211234; - get_spd_sn_ret_sn_idx = 0; - will_return_always(get_spd_sn, CB_SUCCESS); - assert_true(check_if_dimm_changed(spd_cache, &blk)); + get_spd_sn_ret_sn_idx = 0; + will_return_always(get_spd_sn, CB_SUCCESS); + assert_true(check_if_dimm_changed(spd_cache, &blk)); + memset(spd_cache, 0, spd_cache_sz); + } } int main(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/63642 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5ff7fb210b68a4ada18d8387de4ebcd054145 Gerrit-Change-Number: 63642 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Julius Werner (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Arthur Heymans, Yu-Ping Wu, Jianjun Wang. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... Patch Set 16: (1 comment) Patchset: PS9: > So from looking at the code between MTK and QC, I think that ctrl_base == config_base. […] Well, is there anything in the PCIe standard that says those offsets are supposed to be that? Otherwise, we should assume that they can be different for each platform and store them separately. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 16 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 01:05:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022