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Change subject: cezanne: Update CPPC value
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
BUG=b:190420984
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Change subject: mb/google/guybrush/var/nipperkin: turn off WLAN ASPM L1ss
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Change subject: libpayload/defconfig: enable vboot Lib Build
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Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63240/comment/dbe2b14f_0f3af8b1
PS3, Line 9: #3461454
> > We require to build Coreboot (with Depthcharge) outside the ChromeOS SDK, with default configs in […]
Thank you Jakub, Yes, we could implement as you have suggested.
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Change subject: lib: Check for non-existent DIMMs in check_if_dimm_changed
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Patch Set 9:
(1 comment)
Patchset:
PS9:
CB:63643 is the CL for new test case.
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Change subject: mb/google/brya/var/banshee: add the smbus addr for dimm1
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Abandoned
Fixed in CB:63628
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Change subject: mb/google/brya/var/banshee: add the smbus addr for dimm1
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> Hi Frank, yeah that seems like the right thing to do, if banshee does not have those DIMMs, then it […]
HI Tim,
I appreciate your advise.
Let's focus on CB:63628.
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Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 16:
(2 comments)
Patchset:
PS9:
> I think that ctrl_base == config_base
In QC's term, 'config_base' is 'mmio_base'. See CB:57614.
Let me summarize QC and MTK's need here:
```
- MTK: ctrl_base = 0x112f0000
- mmio_base (config_base) = ctrl_base + 0x1000
- ctrl_base + 0x140 (for config space mapping)
- QC: ctrl_base = 0x40000000
- mmio_base = ctrl_base + 0x100000
- mmio_size
- atu_base = ctrl_base + 0x1000
```
I think the main question here is, how much data do we want to pass to payload? To go to extremes we could include all register definitions [1] in sysinfo_t. The other end of the spectrum is to pass minimal data (such as ctrl_base), and leave other offsets (0x1000, 0x140, ...) to be defined in each platform driver in libpayload.
[1] https://review.coreboot.org/c/coreboot/+/57615/52/payloads/libpayload/inclu…
File src/commonlib/bsd/include/commonlib/bsd/cb_err.h:
https://review.coreboot.org/c/coreboot/+/63251/comment/faf201d1_cb7966d6
PS16, Line 18:
Add one tab for alignment.
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