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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63641 )
Change subject: drivers/usb/pci_xhci: Add Sabrina xhci pci devce id
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
File src/drivers/usb/pci_xhci/pci_xhci.c:
https://review.coreboot.org/c/coreboot/+/63641/comment/b3089a31_73c159cd
PS1, Line 262: PCI_DID_AMD_FAM17H_MODELA0H_XHCI2
> Ugh, I really hate maintaining this list. […]
ouch, missed this one when creating the sabrina soc code
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Hello Subrata Banik, Selma Bensaid, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63616
to look at the new patch set (#2).
Change subject: soc/intel/alderlake: Enable Pre Reset CPU Telemetry
......................................................................
soc/intel/alderlake: Enable Pre Reset CPU Telemetry
Insert CSE timestamps to coreboot timestamp table.
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com>
Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63616/2
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Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63631 )
Change subject: soc/intel/{skl, xeon_sp}: Drop SoC specific LPC lock down configuration
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63630/comment/0af8ba96_a03f4089
PS3, Line 103: lpc_set_eiss
This should do the same as fast_spi_lockdown_cfg(). I think that lpc_enable_wp() needs to be added to match.
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Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )
Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 16:
(1 comment)
Patchset:
PS9:
> Hi Shelley, […]
So from looking at the code between MTK and QC, I think that ctrl_base == config_base. Is that correct? I don't have a preference on which name to use. Let's just pick one.
Regarding atu_base and mmio_base....I feel like defining atu_base, mmio_base, mmio_size separately is more flexible than assuming that atu_base is config_base + 0x1000 and mmio_base is config_base + 0x100000. I am, of course, assuming that these offsets can be different across different platforms.
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Julius Werner has submitted this change. ( https://review.coreboot.org/c/qc_blobs/+/62734 )
Change subject: sc7180/boot : Update qclib blobs binaries and release notes
......................................................................
sc7180/boot : Update qclib blobs binaries and release notes
Change-Id: I1dace0db7fd1dcd2f34302885e3fec40b63b7eaf
---
M sc7180/boot/QcLib.elf
M sc7180/boot/Release_Notes.txt
M sc7180/boot/dcb.bin
3 files changed, 23 insertions(+), 0 deletions(-)
Approvals:
Shelley Chen: Verified
Julius Werner: Verified; Looks good to me, approved
diff --git a/sc7180/boot/QcLib.elf b/sc7180/boot/QcLib.elf
index 571c484..bfa4235 100644
--- a/sc7180/boot/QcLib.elf
+++ b/sc7180/boot/QcLib.elf
Binary files differ
diff --git a/sc7180/boot/Release_Notes.txt b/sc7180/boot/Release_Notes.txt
index 3cbda88..536a937 100644
--- a/sc7180/boot/Release_Notes.txt
+++ b/sc7180/boot/Release_Notes.txt
@@ -1,3 +1,26 @@
+=================== Release 00037 ================================
+This Release Notes file covers these blobs:
+ * QcLib.elf
+ * dcb.bin
+
+Version : 00037
+
+Release Date : Mar, 2022
+
+Supported Silicon : SC7180
+
+No special instructions, requirements or dependencies, files must be
+present in this folder to be pulled in during coreboot build
+
+Changes since last version :
+ * Rennell LC | Micron 8GB bitflip issue during WMM fix
+
+Errata : Nothing to report
+
+Toolchain Version : LLVM 12.0.0
+
+ABI Info : see qclib-interface.txt
+
=================== Release 00035 ================================
This Release Notes file covers these blobs:
* QcLib.elf
diff --git a/sc7180/boot/dcb.bin b/sc7180/boot/dcb.bin
index 05c9a5b..217ded3 100644
--- a/sc7180/boot/dcb.bin
+++ b/sc7180/boot/dcb.bin
Binary files differ
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/qc_blobs/+/62734 )
Change subject: sc7180/boot : Update qclib blobs binaries and release notes
......................................................................
Patch Set 1: Verified+1 Code-Review+2
(1 comment)
File sc7180/boot/Release_Notes.txt:
https://review.coreboot.org/c/qc_blobs/+/62734/comment/c91f8714_fac50994
PS1, Line 6: 00037
> In QcLIb37 we have new improved DSF21 for Micron 8GB marginal IO calibration compare to QcLib36
Finally got the source access and been able to confirm that this version is good.
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