coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: mb/google/guybrush: Set BT USB to use GPIO for status
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63559 ) Change subject: mb/google/guybrush: Set BT USB to use GPIO for status ...................................................................... mb/google/guybrush: Set BT USB to use GPIO for status Set the BT USB device to use GPIO for the power status. This causes an ACPI `_STA()` function to be generated that returns the power status of the BT USB device, rather than always returning `0x1`. This `_STA()` function can be used during boot to skip enabling the device (and performing the associated sleep) if the device is already powered on. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp(a)google.com> Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Reviewed-on: https://review.coreboot.org/c/coreboot/+/63559 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index a9b0a15..696e16d 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -321,6 +321,7 @@ # TODO(rrangel): Find data sheet register "enable_delay_ms" = "500" register "enable_off_delay_ms" = "10" + register "use_gpio_for_status" = "true" device ref usb2_port6 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72f6b28671efddfbef53f328d904a05f73f39efa Gerrit-Change-Number: 63559 Gerrit-PatchSet: 8 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: src/acpi/device: Early return in _ON if device already enabled
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63613 ) Change subject: src/acpi/device: Early return in _ON if device already enabled ...................................................................... src/acpi/device: Early return in _ON if device already enabled If the device has enabled `use_gpio_for_status`, then call the `_STA` method in `_ON` to determine if the device is already enabled. If it is already enabled, return early to skip re-enabling the device and performing the associated sleep. This change is necessary since the Linux kernel does not call `_STA` before calling `_ON`. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp(a)google.com> Change-Id: I13aa41766555953b86eded4c72e3b317fe6db5c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63613 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/device.c 1 file changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/acpi/device.c b/src/acpi/device.c index 1df179b..2b085b6 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -670,6 +670,19 @@ /* Method (_ON, 0, Serialized) */ acpigen_write_method_serialized("_ON", 0); + /* Call _STA and early return if the device is already enabled, since the Linux + kernel doesn't check the device status before calling _ON. This avoids + unnecessary delays while booting. */ + if (params->use_gpio_for_status) { + /* Local0 = _STA () */ + acpigen_write_store(); + acpigen_emit_namestring("_STA"); + acpigen_emit_byte(LOCAL0_OP); + /* If (( Local0 == ACPI_POWER_RESOURCE_STATUS_ON_OP)) */ + acpigen_write_if_lequal_op_op(LOCAL0_OP, ACPI_POWER_RESOURCE_STATUS_ON_OP); + acpigen_write_return_op(ZERO_OP); + acpigen_write_if_end(); + } if (reset_gpio) acpigen_enable_tx_gpio(params->reset_gpio); if (enable_gpio) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13aa41766555953b86eded4c72e3b317fe6db5c8 Gerrit-Change-Number: 63613 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_status
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63558 ) Change subject: drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_status ...................................................................... drivers/usb/acpi: acpi_power_res_params: Add use_gpio_for_status Add the member `use_gpio_for_status` to the structure `drivers_usb_acpi_config`, so the `devicetree.cb` can specify it. This field is then used to initialize the corresponding field in the structure `acpi_power_res_params` in `usb_acpi_fill_ssdt_generator()`. The member `acpi_power_res_params::use_gpio_for_status()` is already being used by `acpi_device_add_power_res()` to determine which version of the `_STA()` method to output. BRANCH=None BUG=b:225022810 TEST=Dump SSDT table for guybrush Signed-off-by: Tim Van Patten <timvp(a)google.com> Change-Id: I69eb5f1ad79f3b2980f43dcf4a36585fca198ec9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63558 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 8 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 41481f1..4adffcf 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -66,6 +66,12 @@ * E.g. On a mic: if it is one, it is recording white-noise. */ struct acpi_gpio privacy_gpio; + + /* Write a _STA method that uses the state of the GPIOs to determine if + * the PowerResource is ON or OFF. If this is false, the _STA method + * will always return ON. + */ + bool use_gpio_for_status; }; /* Method to get PLD structure from USB device */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index fb9f7f1..f72129c 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -95,7 +95,8 @@ config->enable_off_delay_ms, NULL, 0, - 0 + 0, + config->use_gpio_for_status }; acpi_device_add_power_res(&power_res_params); } 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69eb5f1ad79f3b2980f43dcf4a36585fca198ec9 Gerrit-Change-Number: 63558 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63494 ) Change subject: coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t ...................................................................... coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Also replace 'struct cbuint64' with 'cb_uint64_t' and remove 'cb_unpack64' in libpayload for compatible with lb_uint64_t. Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/coreinfo/coreboot_module.c M payloads/libpayload/include/coreboot_tables.h M payloads/libpayload/libc/coreboot.c M src/commonlib/include/commonlib/coreboot_tables.h M src/lib/bootmem.c M src/lib/coreboot_table.c M tests/lib/bootmem-test.c M tests/lib/coreboot_table-test.c M util/cbmem/cbmem.c M util/nvramtool/coreboot_tables.h M util/nvramtool/lbtable.c 11 files changed, 59 insertions(+), 117 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c index 87032d5..2c165e1 100644 --- a/payloads/coreinfo/coreboot_module.c +++ b/payloads/coreinfo/coreboot_module.c @@ -94,10 +94,8 @@ mvwprintw(win, row++, 3, " Table: "); } - wprintw(win, "%16.16llx - %16.16llx", - cb_unpack64(cb_info.range[i].start), - cb_unpack64(cb_info.range[i].start) + - cb_unpack64(cb_info.range[i].size) - 1); + wprintw(win, "%16.16llx - %16.16llx", cb_info.range[i].start, + cb_info.range[i].start + cb_info.range[i].size - 1); } return 0; diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index bd23d34..1d38c19 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -91,10 +91,7 @@ CB_TAG_OPTION_CHECKSUM = 0x00cc, }; -struct cbuint64 { - u32 lo; - u32 hi; -}; +typedef __aligned(4) uint64_t cb_uint64_t; struct cb_header { u8 signature[4]; @@ -111,8 +108,8 @@ }; struct cb_memory_range { - struct cbuint64 start; - struct cbuint64 size; + cb_uint64_t start; + cb_uint64_t size; u32 type; }; @@ -271,14 +268,14 @@ struct lb_range { uint32_t tag; uint32_t size; - uint64_t range_start; + cb_uint64_t range_start; uint32_t range_size; }; struct cb_cbmem_tab { uint32_t tag; uint32_t size; - uint64_t cbmem_tab; + cb_uint64_t cbmem_tab; }; struct cb_x86_rom_mtrr { @@ -316,10 +313,10 @@ uint32_t tag; uint32_t size; /* offsets are relative to start of boot media */ - uint64_t fmap_offset; - uint64_t cbfs_offset; - uint64_t cbfs_size; - uint64_t boot_media_size; + cb_uint64_t fmap_offset; + cb_uint64_t cbfs_offset; + cb_uint64_t cbfs_size; + cb_uint64_t boot_media_size; }; @@ -327,7 +324,7 @@ uint32_t tag; uint32_t size; - uint64_t address; + cb_uint64_t address; uint32_t entry_size; uint32_t id; }; @@ -369,7 +366,7 @@ uint32_t tag; uint32_t size; - struct cbuint64 fw_config; + cb_uint64_t fw_config; uint32_t board_id; uint32_t ram_code; uint32_t sku_id; @@ -429,17 +426,12 @@ struct cb_acpi_rsdp { uint32_t tag; uint32_t size; - struct cbuint64 rsdp_pointer; /* Address of the ACPI RSDP */ + cb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ }; /* Helpful inlines */ -static inline u64 cb_unpack64(struct cbuint64 val) -{ - return (((u64) val.hi) << 32) | val.lo; -} - static inline u16 cb_checksum(const void *ptr, unsigned len) { return ipchksum(ptr, len); diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c index 2474df9..cdd6a43 100644 --- a/payloads/libpayload/libc/coreboot.c +++ b/payloads/libpayload/libc/coreboot.c @@ -61,12 +61,8 @@ continue; #endif - info->memrange[info->n_memranges].base = - cb_unpack64(range->start); - - info->memrange[info->n_memranges].size = - cb_unpack64(range->size); - + info->memrange[info->n_memranges].base = range->start; + info->memrange[info->n_memranges].size = range->size; info->memrange[info->n_memranges].type = range->type; info->n_memranges++; @@ -121,7 +117,7 @@ static void cb_parse_board_config(unsigned char *ptr, struct sysinfo_t *info) { struct cb_board_config *const config = (struct cb_board_config *)ptr; - info->fw_config = cb_unpack64(config->fw_config); + info->fw_config = config->fw_config; info->board_id = config->board_id; info->ram_code = config->ram_code; info->sku_id = config->sku_id; @@ -271,7 +267,7 @@ static void cb_parse_rsdp(void *ptr, struct sysinfo_t *info) { const struct cb_acpi_rsdp *cb_acpi_rsdp = ptr; - info->acpi_rsdp = cb_unpack64(cb_acpi_rsdp->rsdp_pointer); + info->acpi_rsdp = cb_acpi_rsdp->rsdp_pointer; } int cb_parse_header(void *addr, int len, struct sysinfo_t *info) diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 01b12f3..206ddb4 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -99,33 +99,11 @@ * 64bit system, a uint64_t would be aligned to 64bit boundaries, * breaking the table format. * - * lb_uint64 will keep 64bit coreboot table values aligned to 32bit - * to ensure compatibility. They can be accessed with the two functions - * below: unpack_lb64() and pack_lb64() - * - * See also: util/lbtdump/lbtdump.c + * lb_uint64_t will keep 64bit coreboot table values aligned to 32bit + * to ensure compatibility. */ -struct lb_uint64 { - uint32_t lo; - uint32_t hi; -}; - -static inline uint64_t unpack_lb64(struct lb_uint64 value) -{ - uint64_t result; - result = value.hi; - result = (result << 32) + value.lo; - return result; -} - -static inline struct lb_uint64 pack_lb64(uint64_t value) -{ - struct lb_uint64 result; - result.lo = (value >> 0) & 0xffffffff; - result.hi = (value >> 32) & 0xffffffff; - return result; -} +typedef __aligned(4) uint64_t lb_uint64_t; struct lb_header { uint8_t signature[4]; /* LBIO */ @@ -148,8 +126,8 @@ }; struct lb_memory_range { - struct lb_uint64 start; - struct lb_uint64 size; + lb_uint64_t start; + lb_uint64_t size; uint32_t type; #define LB_MEM_RAM 1 /* Memory anyone can use */ #define LB_MEM_RESERVED 2 /* Don't use this memory region */ @@ -169,7 +147,7 @@ struct lb_hwrpb { uint32_t tag; uint32_t size; - uint64_t hwrpb; + lb_uint64_t hwrpb; }; struct lb_mainboard { @@ -237,7 +215,7 @@ struct lb_forward { uint32_t tag; uint32_t size; - uint64_t forward; + lb_uint64_t forward; }; /** @@ -295,7 +273,7 @@ uint32_t tag; uint32_t size; - uint64_t physical_address; + lb_uint64_t physical_address; uint32_t x_resolution; uint32_t y_resolution; uint32_t bytes_per_line; @@ -333,7 +311,7 @@ uint32_t tag; uint32_t size; - uint64_t range_start; + lb_uint64_t range_start; uint32_t range_size; }; @@ -343,7 +321,7 @@ uint32_t tag; uint32_t size; - uint64_t cbmem_addr; + lb_uint64_t cbmem_addr; }; struct lb_x86_rom_mtrr { @@ -379,10 +357,10 @@ uint32_t tag; uint32_t size; /* offsets are relative to start of boot media */ - uint64_t fmap_offset; - uint64_t cbfs_offset; - uint64_t cbfs_size; - uint64_t boot_media_size; + lb_uint64_t fmap_offset; + lb_uint64_t cbfs_offset; + lb_uint64_t cbfs_size; + lb_uint64_t boot_media_size; }; /* @@ -392,7 +370,7 @@ uint32_t tag; uint32_t size; - uint64_t address; + lb_uint64_t address; uint32_t entry_size; uint32_t id; }; @@ -461,7 +439,7 @@ uint32_t tag; uint32_t size; - struct lb_uint64 fw_config; + lb_uint64_t fw_config; uint32_t board_id; uint32_t ram_code; uint32_t sku_id; @@ -583,7 +561,7 @@ struct lb_acpi_rsdp { uint32_t tag; uint32_t size; - struct lb_uint64 rsdp_pointer; /* Address of the ACPI RSDP */ + lb_uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ }; #endif diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c index e9d4287..d4462d8 100644 --- a/src/lib/bootmem.c +++ b/src/lib/bootmem.c @@ -110,8 +110,8 @@ bootmem_dump_ranges(); memranges_each_entry(r, &bootmem_os) { - lb_r->start = pack_lb64(range_entry_base(r)); - lb_r->size = pack_lb64(range_entry_size(r)); + lb_r->start = range_entry_base(r); + lb_r->size = range_entry_size(r); lb_r->type = bootmem_to_lb_tag(range_entry_tag(r)); lb_r++; diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3ceab37..c29d308 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -313,7 +313,7 @@ config->board_id = board_id(); config->ram_code = ram_code(); config->sku_id = sku_id(); - config->fw_config = pack_lb64(fw_config); + config->fw_config = fw_config; if (config->board_id != UNDEFINED_STRAPPING_ID) printk(BIOS_INFO, "Board ID: %d\n", config->board_id); @@ -428,7 +428,7 @@ acpi_rsdp = (struct lb_acpi_rsdp *)rec; acpi_rsdp->tag = LB_TAG_ACPI_RSDP; acpi_rsdp->size = sizeof(*acpi_rsdp); - acpi_rsdp->rsdp_pointer = pack_lb64(get_coreboot_rsdp()); + acpi_rsdp->rsdp_pointer = get_coreboot_rsdp(); } size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) diff --git a/tests/lib/bootmem-test.c b/tests/lib/bootmem-test.c index ddd62ae..7bdbf0d 100644 --- a/tests/lib/bootmem-test.c +++ b/tests/lib/bootmem-test.c @@ -177,8 +177,8 @@ required_unused_space_size); for (i = 0; i < lb_mem->size / sizeof(struct lb_memory_range); i++) { - assert_int_equal(unpack_lb64(lb_mem->map[i].start), os_ranges[i].start); - assert_int_equal(unpack_lb64(lb_mem->map[i].size), os_ranges[i].size); + assert_int_equal(lb_mem->map[i].start, os_ranges[i].start); + assert_int_equal(lb_mem->map[i].size, os_ranges[i].size); assert_int_equal(lb_mem->map[i].type, bootmem_to_lb_tag(os_ranges[i].type)); } diff --git a/tests/lib/coreboot_table-test.c b/tests/lib/coreboot_table-test.c index a50dd15..2bf1f61 100644 --- a/tests/lib/coreboot_table-test.c +++ b/tests/lib/coreboot_table-test.c @@ -229,8 +229,8 @@ /* Insert entries for testing */ for (i = 0; i < ARRAY_SIZE(mock_bootmem_ranges); ++i) { struct resource *res = &mock_bootmem_ranges[i]; - lb_r->start = pack_lb64(res->base); - lb_r->size = pack_lb64(res->size); + lb_r->start = res->base; + lb_r->size = res->size; lb_r->type = res->flags; lb_r++; mem->size += sizeof(struct lb_memory_range); @@ -362,18 +362,18 @@ const struct lb_memory *memory = (struct lb_memory *)record; const struct lb_memory_range *range; const struct resource *res; - struct lb_uint64 value; + lb_uint64_t value; for (int i = 0; i < ARRAY_SIZE(mock_bootmem_ranges); ++i) { res = &mock_bootmem_ranges[i]; range = &memory->map[i]; - value = pack_lb64(res->base); + value = res->base; assert_memory_equal(&value, &range->start, - sizeof(struct lb_uint64)); - value = pack_lb64(res->size); + sizeof(lb_uint64_t)); + value = res->size; assert_memory_equal(&value, &range->size, - sizeof(struct lb_uint64)); + sizeof(lb_uint64_t)); assert_int_equal(range->type, res->flags); } break; @@ -475,9 +475,9 @@ const struct lb_board_config *board_config = (struct lb_board_config *)record; - const struct lb_uint64 expected_fw_version = pack_lb64(fw_config_get()); + const lb_uint64_t expected_fw_version = fw_config_get(); assert_memory_equal(&expected_fw_version, &board_config->fw_config, - sizeof(struct lb_uint64)); + sizeof(lb_uint64_t)); assert_int_equal(board_id(), board_config->board_id); assert_int_equal(ram_code(), board_config->ram_code); assert_int_equal(sku_id(), board_config->sku_id); @@ -486,7 +486,7 @@ assert_int_equal(sizeof(struct lb_acpi_rsdp), record->size); const struct lb_acpi_rsdp *acpi_rsdp = (struct lb_acpi_rsdp *)record; - assert_int_equal(ebda_base, unpack_lb64(acpi_rsdp->rsdp_pointer)); + assert_int_equal(ebda_base, acpi_rsdp->rsdp_pointer); break; default: fail_msg("Unexpected tag found in record. Tag ID: 0x%x", record->tag); diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 8add6ec..3af8a25 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -1016,7 +1016,7 @@ return; } - hexdump(unpack_lb64(cbmem.start), unpack_lb64(cbmem.size)); + hexdump(cbmem.start, cbmem.size); } static void rawdump(uint64_t base, uint64_t size) diff --git a/util/nvramtool/coreboot_tables.h b/util/nvramtool/coreboot_tables.h index 1417c19..aafeab4 100644 --- a/util/nvramtool/coreboot_tables.h +++ b/util/nvramtool/coreboot_tables.h @@ -45,33 +45,11 @@ * 64bit system, a uint64_t would be aligned to 64bit boundaries, * breaking the table format. * - * lb_uint64 will keep 64bit coreboot table values aligned to 32bit - * to ensure compatibility. They can be accessed with the two functions - * below: unpack_lb64() and pack_lb64() - * - * See also: util/lbtdump/lbtdump.c + * lb_uint64_t will keep 64bit coreboot table values aligned to 32bit + * to ensure compatibility. */ -struct lb_uint64 { - uint32_t lo; - uint32_t hi; -}; - -static inline uint64_t unpack_lb64(struct lb_uint64 value) -{ - uint64_t result; - result = value.hi; - result = (result << 32) + value.lo; - return result; -} - -static inline struct lb_uint64 pack_lb64(uint64_t value) -{ - struct lb_uint64 result; - result.lo = (value >> 0) & 0xffffffff; - result.hi = (value >> 32) & 0xffffffff; - return result; -} +typedef __attribute__((aligned(4))) uint64_t lb_uint64_t; struct lb_header { union { @@ -101,8 +79,8 @@ #define LB_TAG_MEMORY 0x0001 struct lb_memory_range { - struct lb_uint64 start; - struct lb_uint64 size; + lb_uint64_t start; + lb_uint64_t size; uint32_t type; #define LB_MEM_RAM 1 /* Memory anyone can use */ #define LB_MEM_RESERVED 2 /* Don't use this memory region */ diff --git a/util/nvramtool/lbtable.c b/util/nvramtool/lbtable.c index fd6c9ec..6993cc0 100644 --- a/util/nvramtool/lbtable.c +++ b/util/nvramtool/lbtable.c @@ -632,8 +632,8 @@ break; } - size = unpack_lb64(ranges[i].size); - start = unpack_lb64(ranges[i].start); + size = ranges[i].size; + start = ranges[i].start; end = start + size - 1; printf("%s memory:\n" " from physical addresses 0x%016" PRIx64 -- To view, visit https://review.coreboot.org/c/coreboot/+/63494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Gerrit-Change-Number: 63494 Gerrit-PatchSet: 9 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/skyrim: Inject SPDs into APCB
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63600 ) Change subject: mb/google/skyrim: Inject SPDs into APCB ...................................................................... mb/google/skyrim: Inject SPDs into APCB Update the build scripts to inject variant specific SPDs into APCB. BUG=None TEST=Build and boot to OS in Skyrim boards with all the concerned memory parts. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/63600 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/Makefile.inc 1 file changed, 13 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Makefile.inc b/src/mainboard/google/skyrim/Makefile.inc index e66f7c9..f76a961 100644 --- a/src/mainboard/google/skyrim/Makefile.inc +++ b/src/mainboard/google/skyrim/Makefile.inc @@ -16,8 +16,19 @@ ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin),) $(info APCB sources present.) -APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin -APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin + +LIB_SPD_DEPS = $(SPD_SOURCES) + +APCB_SOURCES = $(obj)/APCB_SBR_D5.gen +APCB_SOURCES_RECOVERY = $(obj)/APCB_SBR_D5.gen + +$(obj)/APCB_SBR_D5.gen: $(SPD_SOURCES) \ + $(APCB_V3_EDIT_TOOL) \ + $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin + $(APCB_V3_EDIT_TOOL) $(MAINBOARD_BLOBS_DIR)/APCB_SBR_D5.bin \ + $(obj)/APCB_SBR_D5.gen \ + --spd_sources $(SPD_SOURCES) \ + --mem_type 'lp5' else $(info APCB sources not found. Skipping APCB.) endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b3f6f248d54681c6f55c00660d1f2988ae906ba Gerrit-Change-Number: 63600 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/skyrim/var/skyrim: Add supported memory parts
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63599 ) Change subject: mb/google/skyrim/var/skyrim: Add supported memory parts ...................................................................... mb/google/skyrim/var/skyrim: Add supported memory parts Add supported memory parts and generate the associated DRAM part ID. Also for MT62F2G32D8DR-031 WT:B memory part, add a custom SPD that configures the DRAM speed at 5500 MHz. Use this custom SPD until that part can operate at full speed (i.e. 6400 MHz). BUG=None TEST=Build Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63599 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Robert Zieba <robertzieba(a)google.com> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- A src/mainboard/google/skyrim/variants/skyrim/Makefile.inc A src/mainboard/google/skyrim/variants/skyrim/memory/Makefile.inc A src/mainboard/google/skyrim/variants/skyrim/memory/dram_id.generated.txt A src/mainboard/google/skyrim/variants/skyrim/memory/mem_parts_used.txt A src/mainboard/google/skyrim/variants/skyrim/memory/spd-MT62F2G32D8DR-031.hex 5 files changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve Robert Zieba: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/variants/skyrim/Makefile.inc b/src/mainboard/google/skyrim/variants/skyrim/Makefile.inc new file mode 100644 index 0000000..88e75bd --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./memory diff --git a/src/mainboard/google/skyrim/variants/skyrim/memory/Makefile.inc b/src/mainboard/google/skyrim/variants/skyrim/memory/Makefile.inc new file mode 100644 index 0000000..35975c7 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/memory/Makefile.inc @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen SBR lp5 src/mainboard/google/skyrim/variants/skyrim/memory/ src/mainboard/google/skyrim/variants/skyrim/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 1(0b0001) Parts = MT62F1G32D4DR-031 WT:B +SPD_SOURCES += src/mainboard/google/skyrim/variants/skyrim/memory/spd-MT62F2G32D8DR-031.hex # ID = 2(0b0010) Parts = MT62F2G32D8DR-031 WT:B diff --git a/src/mainboard/google/skyrim/variants/skyrim/memory/dram_id.generated.txt b/src/mainboard/google/skyrim/variants/skyrim/memory/dram_id.generated.txt new file mode 100644 index 0000000..b4115ed --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/memory/dram_id.generated.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen SBR lp5 src/mainboard/google/skyrim/variants/skyrim/memory/ src/mainboard/google/skyrim/variants/skyrim/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) +MT62F1G32D4DR-031 WT:B 1 (0001) +MT62F2G32D8DR-031 WT:B 2 (0010) diff --git a/src/mainboard/google/skyrim/variants/skyrim/memory/mem_parts_used.txt b/src/mainboard/google/skyrim/variants/skyrim/memory/mem_parts_used.txt new file mode 100644 index 0000000..bd84cbf --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/memory/mem_parts_used.txt @@ -0,0 +1,3 @@ +MT62F512M32D2DR-031 WT:B, +MT62F1G32D4DR-031 WT:B, +MT62F2G32D8DR-031 WT:B,2,spd-MT62F2G32D8DR-031.hex diff --git a/src/mainboard/google/skyrim/variants/skyrim/memory/spd-MT62F2G32D8DR-031.hex b/src/mainboard/google/skyrim/variants/skyrim/memory/spd-MT62F2G32D8DR-031.hex new file mode 100644 index 0000000..01a5734 --- /dev/null +++ b/src/mainboard/google/skyrim/variants/skyrim/memory/spd-MT62F2G32D8DR-031.hex @@ -0,0 +1,32 @@ +23 11 13 0E 85 21 F9 18 00 40 00 00 09 02 00 00 +00 00 03 00 00 00 00 00 2C 00 90 A8 90 90 06 C0 +03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 C9 00 F4 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63599 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id87e79f5d6187d57d74487841c09aa309f1450b4 Gerrit-Change-Number: 63599 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63598 ) Change subject: util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic ...................................................................... util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic APCB edit tool edits APCBs with LP4 specific SPDs. Introduce an option to support different SPD magic so that the tool can be used to edit APCBs with LP5 specific SPDs. BUG=None TEST=Build Skyrim board with LP5 specific SPDs. Build Guybrush board with LP4 specific SPDs. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63598 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/apcb/apcb_v3_edit.py 1 file changed, 14 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/util/apcb/apcb_v3_edit.py b/util/apcb/apcb_v3_edit.py index 9a70bac..140b232 100755 --- a/util/apcb/apcb_v3_edit.py +++ b/util/apcb/apcb_v3_edit.py @@ -14,8 +14,10 @@ # Byte 0 = 0x23 = 512 bytes total / 384 bytes used # Byte 1 = 0x11 = Revision 1.1 # Byte 2 = 0x11 = LPDDR4X SDRAM +# = 0x13 = LP5 SDRAM # Byte 3 = 0x0E = Non-DIMM Solution -SPD_MAGIC = bytes.fromhex('2311110E') +LP4_SPD_MAGIC = bytes.fromhex('2311110E') +LP5_SPD_MAGIC = bytes.fromhex('2311130E') EMPTY_SPD = b'\x00' * 512 spd_ssp_struct_fmt = '??B?IIBBBxIIBBBx' @@ -47,6 +49,11 @@ '--spd_sources', nargs='+', help='List of SPD sources') + parser.add_argument( + '--mem_type', + type=str, + default='lp4', + help='Memory type [lp4|lp5]. Default = lp4') return parser.parse_args() @@ -62,6 +69,8 @@ def main(): + spd_magic = LP4_SPD_MAGIC + args = parseargs() print(f'Reading input APCB from {args.apcb_in}') @@ -75,6 +84,9 @@ print(f'Using SPD Sources = {args.spd_sources}') + if args.mem_type == 'lp5': + spd_magic = LP5_SPD_MAGIC + spds = [] for spd_source in args.spd_sources: with open(spd_source, 'rb') as f: @@ -85,7 +97,7 @@ spd_offset = 0 instance = 0 while True: - spd_offset = apcb.find(SPD_MAGIC, spd_offset) + spd_offset = apcb.find(spd_magic, spd_offset) if spd_offset < 0: print('No more SPD magic numbers in APCB') break -- To view, visit https://review.coreboot.org/c/coreboot/+/63598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708 Gerrit-Change-Number: 63598 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/spd_tools/part_id_gen: Support Sabrina SoC
by Felix Held (Code Review) 15 Apr '22

15 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63597 ) Change subject: util/spd_tools/part_id_gen: Support Sabrina SoC ...................................................................... util/spd_tools/part_id_gen: Support Sabrina SoC Add support to generate DRAM part ID for boards using Sabrina SoC. BUG=None TEST=Generate DRAM part ID for Skyrim mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Robert Zieba <robertzieba(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M util/spd_tools/src/part_id_gen/part_id_gen.go 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Robert Zieba: Looks good to me, but someone else must approve diff --git a/util/spd_tools/src/part_id_gen/part_id_gen.go b/util/spd_tools/src/part_id_gen/part_id_gen.go index edbad9c..eef7ee3 100644 --- a/util/spd_tools/src/part_id_gen/part_id_gen.go +++ b/util/spd_tools/src/part_id_gen/part_id_gen.go @@ -40,6 +40,7 @@ "JSL", "PCO", "CZN", + "SBR", } var supportedMemTechs = [...]string{ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986 Gerrit-Change-Number: 63597 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Wonkyu Kim (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Subrata Banik, Angel Pons. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/63615/comment/37c35866_817b522e PS3, Line 23: static > nit: static not needed Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 20:37:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/var/crota: Add Kconfig for TPM I2C bus
by Paul Menzel (Code Review) 14 Apr '22

14 Apr '22

Attention is currently required from: Terry Chen, Raihow Shi. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63617 ) Change subject: mb/google/brya/var/crota: Add Kconfig for TPM I2C bus ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63617/comment/15d8a943_84685d5f PS5, Line 7: mb/google/brya/var/crota: Add Kconfig for TPM I2C bus Maybe: Kconfig: Select TPM I2C bus driver -- To view, visit https://review.coreboot.org/c/coreboot/+/63617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Gerrit-Change-Number: 63617 Gerrit-PatchSet: 5 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Thu, 14 Apr 2022 20:31:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022