coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names
by Michał Żygowski (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63655 ) Change subject: soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names ...................................................................... soc/intel/alderlake/chip.c: Add missing ADL-S USB ports ACPI names ADL-S has more USB ports than mobile chipsets. Add missing ACPI names. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b --- M src/soc/intel/alderlake/chip.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63655/1 diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 4bb7aa7..bb7142c 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -43,6 +43,10 @@ case 7: return "HS08"; case 8: return "HS09"; case 9: return "HS10"; + case 10: return "HS11"; + case 11: return "HS12"; + case 12: return "HS13"; + case 13: return "HS14"; } break; case 3: @@ -52,6 +56,12 @@ case 1: return "SS02"; case 2: return "SS03"; case 3: return "SS04"; + case 4: return "SS05"; + case 5: return "SS06"; + case 6: return "SS07"; + case 7: return "SS08"; + case 8: return "SS09"; + case 9: return "SS10"; } break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b Gerrit-Change-Number: 63655 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/alderlake: Add ADL-S PCIe support
by Michał Żygowski (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Tim Wawrzynczak. Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63654 ) Change subject: soc/alderlake: Add ADL-S PCIe support ...................................................................... soc/alderlake: Add ADL-S PCIe support Extend the code to support ADL-S PCIe Root Ports. Based on DOC #619362 and #619501. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 --- M src/soc/intel/alderlake/chip.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/pci_devs.h M src/soc/intel/alderlake/pcie_rp.c 4 files changed, 108 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/63654/1 diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 699b39d..4bb7aa7 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -63,6 +63,7 @@ switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; + case SA_DEVFN_CPU_PCIE1_1: return "PEG3"; case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; case SA_DEVFN_IGD: return "GFX0"; @@ -98,6 +99,25 @@ case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_PCIE17: return "RP17"; + case PCH_DEVFN_PCIE18: return "RP18"; + case PCH_DEVFN_PCIE19: return "RP19"; + case PCH_DEVFN_PCIE20: return "RP20"; + case PCH_DEVFN_PCIE21: return "RP21"; + case PCH_DEVFN_PCIE22: return "RP22"; + case PCH_DEVFN_PCIE23: return "RP23"; + case PCH_DEVFN_PCIE24: return "RP24"; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + /* Avoid conflicts with PCH-N eMMC */ + case PCH_DEVFN_PCIE25: return "RP25"; + case PCH_DEVFN_PCIE26: return "RP26"; + case PCH_DEVFN_PCIE27: return "RP27"; + case PCH_DEVFN_PCIE28: return "RP28"; +#endif case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index fa4104e..0d72484 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -214,8 +214,38 @@ FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D), +#endif }, }, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + { + .slot = PCH_DEV_SLOT_PCIE_2, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCH_DEV_SLOT_PCIE_3, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE25, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE26, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE27, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE28, PCI_INT_D, PIRQ_D), + }, + }, +#endif { .slot = PCH_DEV_SLOT_SIO5, .fns = { diff --git a/src/soc/intel/alderlake/include/soc/pci_devs.h b/src/soc/intel/alderlake/include/soc/pci_devs.h index b7196df..8041bc5 100644 --- a/src/soc/intel/alderlake/include/soc/pci_devs.h +++ b/src/soc/intel/alderlake/include/soc/pci_devs.h @@ -27,6 +27,7 @@ #define SA_DEV_SLOT_CPU_1 0x01 #define SA_DEVFN_CPU_PCIE1_0 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 0) +#define SA_DEVFN_CPU_PCIE1_1 PCI_DEVFN(SA_DEV_SLOT_CPU_1, 1) #define SA_DEV_SLOT_IGD 0x02 #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) @@ -195,10 +196,47 @@ #define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1) #define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2) #define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3) +#define PCH_DEVFN_PCIE13 _PCH_DEVFN(PCIE_1, 4) +#define PCH_DEVFN_PCIE14 _PCH_DEVFN(PCIE_1, 5) +#define PCH_DEVFN_PCIE15 _PCH_DEVFN(PCIE_1, 6) +#define PCH_DEVFN_PCIE16 _PCH_DEVFN(PCIE_1, 7) #define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0) #define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1) #define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2) #define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3) +#define PCH_DEV_PCIE13 _PCH_DEV(PCIE_1, 4) +#define PCH_DEV_PCIE14 _PCH_DEV(PCIE_1, 5) +#define PCH_DEV_PCIE15 _PCH_DEV(PCIE_1, 6) +#define PCH_DEV_PCIE16 _PCH_DEV(PCIE_1, 7) + + +#define PCH_DEV_SLOT_PCIE_2 0x1b +#define PCH_DEVFN_PCIE17 _PCH_DEVFN(PCIE_2, 0) +#define PCH_DEVFN_PCIE18 _PCH_DEVFN(PCIE_2, 1) +#define PCH_DEVFN_PCIE19 _PCH_DEVFN(PCIE_2, 2) +#define PCH_DEVFN_PCIE20 _PCH_DEVFN(PCIE_2, 3) +#define PCH_DEVFN_PCIE21 _PCH_DEVFN(PCIE_2, 4) +#define PCH_DEVFN_PCIE22 _PCH_DEVFN(PCIE_2, 5) +#define PCH_DEVFN_PCIE23 _PCH_DEVFN(PCIE_2, 6) +#define PCH_DEVFN_PCIE24 _PCH_DEVFN(PCIE_2, 7) +#define PCH_DEV_PCIE17 _PCH_DEV(PCIE_2, 0) +#define PCH_DEV_PCIE18 _PCH_DEV(PCIE_2, 1) +#define PCH_DEV_PCIE19 _PCH_DEV(PCIE_2, 2) +#define PCH_DEV_PCIE20 _PCH_DEV(PCIE_2, 3) +#define PCH_DEV_PCIE21 _PCH_DEV(PCIE_2, 4) +#define PCH_DEV_PCIE22 _PCH_DEV(PCIE_2, 5) +#define PCH_DEV_PCIE23 _PCH_DEV(PCIE_2, 6) +#define PCH_DEV_PCIE24 _PCH_DEV(PCIE_2, 7) + +#define PCH_DEV_SLOT_PCIE_3 0x1a +#define PCH_DEVFN_PCIE25 _PCH_DEVFN(PCIE_3, 0) +#define PCH_DEVFN_PCIE26 _PCH_DEVFN(PCIE_3, 1) +#define PCH_DEVFN_PCIE27 _PCH_DEVFN(PCIE_3, 2) +#define PCH_DEVFN_PCIE28 _PCH_DEVFN(PCIE_3, 3) +#define PCH_DEV_PCIE25 _PCH_DEV(PCIE_3, 0) +#define PCH_DEV_PCIE26 _PCH_DEV(PCIE_3, 1) +#define PCH_DEV_PCIE27 _PCH_DEV(PCIE_3, 2) +#define PCH_DEV_PCIE28 _PCH_DEV(PCIE_3, 3) #define PCH_DEV_SLOT_SIO5 0x1e #define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0) diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index 1193047..6bbe298 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -20,11 +20,22 @@ { 0 } }; +static const struct pcie_rp_group pch_s_rp_groups[] = { + { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, + { .slot = PCH_DEV_SLOT_PCIE_3, .count = 4, .lcap_port_base = 1 }, + { 0 } +}; + const struct pcie_rp_group *get_pch_pcie_rp_table(void) { if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) return pch_m_rp_groups; + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + return pch_s_rp_groups; + return pch_lp_rp_groups; /* Valid for PCH-P and PCH-N */ } @@ -50,6 +61,12 @@ { 0 } }; +static const struct pcie_rp_group cpu_s_rp_groups[] = { + { .slot = SA_DEV_SLOT_CPU_6, .start = 0, .count = 1, .lcap_port_base = 1 }, + { .slot = SA_DEV_SLOT_CPU_1, .start = 0, .count = 2, .lcap_port_base = 1 }, + { 0 } +}; + const struct pcie_rp_group *get_cpu_pcie_rp_table(void) { if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_M)) @@ -58,6 +75,9 @@ if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)) return cpu_n_rp_groups; + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + return cpu_s_rp_groups; + return cpu_rp_groups; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23 Gerrit-Change-Number: 63654 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: include/smbios.h: Add PCIe Gen5 slot type definitions
by Michał Żygowski (Code Review) 15 Apr '22

15 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63653 ) Change subject: include/smbios.h: Add PCIe Gen5 slot type definitions ...................................................................... include/smbios.h: Add PCIe Gen5 slot type definitions Add PCI Express Gen5 slot type definitions from DMTF SMBIOS specification 3.5.0. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I46e07feb23bdd6ac9f145a649b77a88db1c08624 --- M src/include/smbios.h 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/63653/1 diff --git a/src/include/smbios.h b/src/include/smbios.h index c11fc6c..4e53771 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -730,7 +730,13 @@ SlotTypePciExpressGen4x2 = 0xBA, SlotTypePciExpressGen4x4 = 0xBB, SlotTypePciExpressGen4x8 = 0xBC, - SlotTypePciExpressGen4x16 = 0xBD + SlotTypePciExpressGen4x16 = 0xBD, + SlotTypePciExpressGen5 = 0xBE, + SlotTypePciExpressGen5x1 = 0xBF, + SlotTypePciExpressGen5x2 = 0xC0, + SlotTypePciExpressGen5x4 = 0xC1, + SlotTypePciExpressGen5x8 = 0xC2, + SlotTypePciExpressGen5x16 = 0xC3, }; /* System Slots - Slot Data Bus Width. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63653 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e07feb23bdd6ac9f145a649b77a88db1c08624 Gerrit-Change-Number: 63653 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: add chipset devicetree for ADL-S
by Michał Żygowski (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Michał Kopeć. Michał Żygowski has uploaded a new patch set (#9) to the change originally created by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/63493 ) Change subject: soc/intel/alderlake: add chipset devicetree for ADL-S ...................................................................... soc/intel/alderlake: add chipset devicetree for ADL-S Add chipset devicetree and power limits for AlderLake-S platform. Based on Intel docs #619501 and #619362. Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/chip.h A src/soc/intel/alderlake/chipset_pch_s.cb M src/soc/intel/alderlake/fsp_params.c 4 files changed, 213 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63493/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/63493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807 Gerrit-Change-Number: 63493 Gerrit-PatchSet: 9 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement IOC driver
by Wonkyu Kim (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 ) Change subject: soc/intel/common: Implement IOC driver ...................................................................... Patch Set 17: (2 comments) File src/soc/intel/common/block/ioc/ioc.c: https://review.coreboot.org/c/coreboot/+/63198/comment/17e82843_5ddfa746 PS17, Line 12: get_mchbar > I would have written this logic as below […] You mean move get_mchbar api in systemagent_early.c and implement set mch bar incase it's not enabled? https://review.coreboot.org/c/coreboot/+/63198/comment/cc8bbfad_7b3826a7 PS17, Line 16: if( > if ( Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 17 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 16:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/{block, pch}: Migrate GPMR driver
by Wonkyu Kim (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63471 ) Change subject: soc/intel/cmn/{block, pch}: Migrate GPMR driver ...................................................................... Patch Set 13: (2 comments) File src/soc/intel/common/block/lpc/lpc_lib.c: https://review.coreboot.org/c/coreboot/+/63471/comment/602881cb_7b23f0bf PS13, Line 29: gpmr_write32 > This write was changed from 16 bits to 32 bits, is it OK? Register offset is 4 byte aligned. So it's ok to use 32bit access. https://review.coreboot.org/c/coreboot/+/63471/comment/cdbc0535_2baa7610 PS13, Line 47: gpmr_write32 > Ditto. Register offset is 4 byte aligned. So it's ok to use 32bit access. -- To view, visit https://review.coreboot.org/c/coreboot/+/63471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Gerrit-Change-Number: 63471 Gerrit-PatchSet: 13 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 15:58:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/{block, pch}: Migrate GPMR driver
by Wonkyu Kim (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Ravishankar Sarawadi, Angel Pons, Nick Vaccaro, Tim Wawrzynczak. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63471 ) Change subject: soc/intel/cmn/{block, pch}: Migrate GPMR driver ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63471/comment/354a0098_883b116e PS13, Line 40: gpmr_or32(GPMR_GCS, GPMR_GCS_BILD); : : /* : * Set Secure Register Lock (SRL) bit in DMI control register to lock : * DMI configuration. : */ : gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); > Does MTL have these registers in MCHBAR? Yes. -- To view, visit https://review.coreboot.org/c/coreboot/+/63471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 Gerrit-Change-Number: 63471 Gerrit-PatchSet: 13 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 15:57:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Enable tablet mode switch
by Rob Barnes (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Diana Zigterman, Kenneth Chan, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63649 ) Change subject: mb/google/guybrush: Enable tablet mode switch ...................................................................... Patch Set 3: -Code-Review (1 comment) File src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h: https://review.coreboot.org/c/coreboot/+/63649/comment/67d14853_bb47f791 PS3, Line 65: #define EC_ENABLE_TBMC_DEVICE This should be moved to dewatt/include/variant/ec.h -- To view, visit https://review.coreboot.org/c/coreboot/+/63649 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ae31f314ee42474a1252be458ab383ec6036d85 Gerrit-Change-Number: 63649 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Diana Zigterman <dzigterman(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Diana Zigterman <dzigterman(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 15:55:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask/variants/moli: use specific VBT files
by Tim Wawrzynczak (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: YH Lin, Paul Menzel, Raihow Shi, Felix Held. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63604 ) Change subject: mb/google/brask/variants/moli: use specific VBT files ...................................................................... Patch Set 11: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63604/comment/5cef5829_ea17c84e PS11, Line 7: use specific VBT files suggestion: `Pick VBT based on FW_CONFIG` https://review.coreboot.org/c/coreboot/+/63604/comment/f491c1e0_e360ceda PS11, Line 9: DP, nit: spaces after a comma, `for HDMI, DP, and ABSENT ` -- To view, visit https://review.coreboot.org/c/coreboot/+/63604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8fbef1467605505459fce264697f670591c81e Gerrit-Change-Number: 63604 Gerrit-PatchSet: 11 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 15:49:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card
by Tim Wawrzynczak (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Chen Wisley, Wisley Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63648 ) Change subject: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Can you please update the bug with more information about the power saving feature? -- To view, visit https://review.coreboot.org/c/coreboot/+/63648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Gerrit-Change-Number: 63648 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 15:44:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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