coreboot-gerrit April 2022

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Change in coreboot[master]: arch/x86: Add support for catching null deferences through debug regs
by Robert Zieba (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Robert Zieba. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63657 to look at the new patch set (#3). Change subject: arch/x86: Add support for catching null deferences through debug regs ...................................................................... arch/x86: Add support for catching null deferences through debug regs This commit adds support for catching null deferences and execution through x86's debug registers. This is particularly useful when running 32-bit coreboot as paging is not enabled to catch these through page faults. To support this feature three new configs have been added: DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and DEBUG_NULL_DEREF_HALT. BUG=b:223902046 TEST=Ran on nipperkin device, verifying that HW breakpoints work as expected Change-Id: I113590689046a13c2a552741bbfe7668a834354a Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/breakpoint.c M src/arch/x86/exception.c A src/arch/x86/include/arch/breakpoint.h A src/arch/x86/include/arch/null_breakpoint.h A src/arch/x86/null_breakpoint.c 7 files changed, 422 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/63657/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I113590689046a13c2a552741bbfe7668a834354a Gerrit-Change-Number: 63657 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Add support for catching null deferences through debug regs
by Robert Zieba (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Robert Zieba. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63657 to look at the new patch set (#2). Change subject: arch/x86: Add support for catching null deferences through debug regs ...................................................................... arch/x86: Add support for catching null deferences through debug regs This commit adds support for catching null deferences and execution through x86's debug registers. This is particularly useful when running 32-bit coreboot as paging is not enabled to catch these through page faults. To support this feature three new configs have been added: DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and DEBUG_NULL_DEREF_HALT. BUG=b:223902046 TEST=Ran on nipperkin device, verifying that HW breakpoints work as expected Change-Id: I113590689046a13c2a552741bbfe7668a834354a Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/breakpoint.c M src/arch/x86/exception.c A src/arch/x86/include/arch/breakpoint.h A src/arch/x86/include/arch/null_breakpoint.h A src/arch/x86/null_breakpoint.c 7 files changed, 422 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/63657/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I113590689046a13c2a552741bbfe7668a834354a Gerrit-Change-Number: 63657 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/common/../systemagent: Enable MCHBAR in bootblock
by Wonkyu Kim (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Enable MCHBAR in bootblock ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/09404e37_8ffd6406 PS4, Line 10: As there is no harm to enable : MCHBAR from bootblock even in existing plaforms > > > > Enabling MCHBAR takes a PCI config register write or two, so size isn't a concern. […] IOC read/write requires MCHBAR. https://review.coreboot.org/c/coreboot/+/63198/17/src/soc/intel/common/bloc… If we have concern for existing platform, we can move api(get_mchbar) and initialize MCHBAR from the API as comment from ioc.c change. WDYT? -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 4 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 15 Apr 2022 17:36:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/update_microcode: Make ucode update more generic
by Fred Reitberger (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Angel Pons, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63589 ) Change subject: soc/amd/common/block/update_microcode: Make ucode update more generic ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Why doesn't the microcode header have a size field? I don't know why, but there is no size field in the header. -- To view, visit https://review.coreboot.org/c/coreboot/+/63589 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84a2480cf8274d53ffdab7864135c1bf001241e6 Gerrit-Change-Number: 63589 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 15 Apr 2022 17:18:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add support for catching null deferences through debug regs
by Robert Zieba (Code Review) 15 Apr '22

15 Apr '22

Robert Zieba has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63657 ) Change subject: arch/x86: Add support for catching null deferences through debug regs ...................................................................... arch/x86: Add support for catching null deferences through debug regs This commit adds support for catching null deferences and execution through x86's debug registers. This is particularly useful when running 32-bit coreboot as paging is not enabled to catch these through page faults. To support this feature three new configs have been added: DEBUG_HW_BREAKPOINTS, DEBUG_NULL_DEREF_BREAKPOINTS and DEBUG_NULL_DEREF_HALT. BUG=b:223902046 TEST=Ran on nipperkin device, verifying that HW breakpoints work as expected Change-Id: I113590689046a13c2a552741bbfe7668a834354a Signed-off-by: Robert Zieba <robertzieba(a)google.com> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/breakpoint.c M src/arch/x86/exception.c A src/arch/x86/include/arch/breakpoint.h A src/arch/x86/include/arch/null_breakpoint.h A src/arch/x86/null_breakpoint.c 7 files changed, 422 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/63657/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e9fce50..9491686 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -320,6 +320,28 @@ string default "src/arch/x86/memlayout.ld" +config DEBUG_HW_BREAKPOINTS + bool + default y + help + Enables support for hardware data and instruction breakpoints through + the x86 debug registers + +config DEBUG_NULL_DEREF_BREAKPOINTS + bool + default y + depends on DEBUG_HW_BREAKPOINTS + help + Enables support for catching null deferences and instruction execution + +config DEBUG_NULL_DEREF_HALT + bool + default n + depends on DEBUG_NULL_DEREF_BREAKPOINTS + help + When enabled null deferences and instruction fetches will halt execution. + Otherwise an error will be printed. + # Some EC need an "EC firmware pointer" (a data structure hinting the address # of its firmware blobs) being put at a fixed position. Its space # (__section__(".ecfw_ptr")) should be reserved if it lies in the range of a diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 458bcc6..b85b5e5 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -234,6 +234,8 @@ ramstage-y += c_exit.S ramstage-y += cpu.c ramstage-y += cpu_common.c +ramstage-$(CONFIG_DEBUG_HW_BREAKPOINTS) += breakpoint.c +ramstage-$(CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS) += null_breakpoint.c ramstage-y += ebda.c ramstage-y += exception.c ramstage-y += idt.S diff --git a/src/arch/x86/breakpoint.c b/src/arch/x86/breakpoint.c new file mode 100644 index 0000000..e50b1c0 --- /dev/null +++ b/src/arch/x86/breakpoint.c @@ -0,0 +1,288 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/registers.h> +#include <arch/breakpoint.h> +#include <console/console.h> +#include <types.h> + +#define DEBUG_REGISTER_COUNT 4 + +/* Each enable field is 2 bits and starts at bit 0 */ +#define DEBUG_CTRL_ENABLE_SHIFT(index) (2 * index) +#define DEBUG_CTRL_ENABLE_MASK(index) (0x3 << DEBUG_CTRL_ENABLE_SHIFT(index)) +#define DEBUG_CTRL_ENABLE(index, enable) (enable << DEBUG_CTRL_ENABLE_SHIFT(index)) + +/* Each breakpoint has a length and type, each is two bits and start at bit 16 */ +#define DEBUG_CTRL_LT_SHIFT(index) (4 * index + 16) +#define DEBUG_CTRL_LT_MASK(index) (0xf << DEBUG_CTRL_LT_SHIFT(index)) +#define DEBUG_CTRL_LT(index, len, type) ((((len) << 2 | (type))) << DEBUG_CTRL_LT_SHIFT(index)) + +/* Type takes up the lower two bits */ +#define DEBUG_CTRL_GET_TYPE(index, value) (((value) & DEBUG_CTRL_ENABLE_MASK(index)) \ + >> (DEBUG_CTRL_ENABLE_SHIFT(index) + 2)) + +/* Each field is one bit, starting at bit 0 */ +#define DEBUG_STATUS_BP_HIT_MASK(index) (1 << index) +#define DEBUG_STATUS_GET_BP_HIT(index, value) ((value & DEBUG_STATUS_BP_HIT_MASK(index)) \ + >> index) + +/* Breakpoint lengths values */ +#define DEBUG_CTRL_LEN_1 0x0 +#define DEBUG_CTRL_LEN_2 0x1 +#define DEBUG_CTRL_LEN_8 0x2 +#define DEBUG_CTRL_LEN_4 0x3 + +/* Breakpoint types values */ +#define DEBUG_CTRL_INSTR 0x0 +#define DEBUG_CTRL_WRITE 0x1 +#define DEBUG_CTRL_IO_RW 0x2 +#define DEBUG_CTRL_RW 0x3 + +/* Breakpoint enable values */ +#define DEBUG_CTRL_ENABLE_LOCAL 0x1 +#define DEBUG_CTRL_ENABLE_GLOBAL 0x2 + +/* eflags/rflags bit to continue execution after hitting an instruction breakpoint */ +#define FLAGS_RESUME (1 << 16) + +static bool allocated_breakpoints[DEBUG_REGISTER_COUNT] = { 0, 0, 0, 0 }; +static breakpoint_handler handlers[DEBUG_REGISTER_COUNT] = { NULL, NULL, NULL, NULL}; + +static inline uintptr_t debug_read_addr_reg(int index) { + uintptr_t ret = ~0x0; + switch (index) { + case 0: + asm("mov %%dr0, %0" : "=r"(ret)); + break; + + case 1: + asm("mov %%dr1, %0" : "=r"(ret)); + break; + + case 2: + asm("mov %%dr2, %0" : "=r"(ret)); + break; + + case 3: + asm("mov %%dr3, %0" : "=r"(ret)); + break; + + default: + break; + } + + return ret; +} + +static inline void debug_write_addr_reg(int index, uintptr_t value) { + switch (index) { + case 0: + asm("mov %0, %%dr0" :: "r"(value)); + break; + + case 1: + asm("mov %0, %%dr1" :: "r"(value)); + break; + + case 2: + asm("mov %0, %%dr2" :: "r"(value)); + break; + + case 3: + asm("mov %0, %%dr3" :: "r"(value)); + break; + + default: + break; + } +} + +static inline uintptr_t debug_read_status(void) { + uintptr_t ret = 0; + asm("mov %%dr6, %0" : "=r"(ret)); + return ret; +} + +static inline void debug_write_status(uintptr_t value) { + asm("mov %0, %%dr6" :: "r"(value)); +} + +static inline uintptr_t debug_read_control(void) { + uintptr_t ret = 0; + asm("mov %%dr7, %0" : "=r"(ret)); + return ret; +} + +static inline void debug_write_control(uintptr_t value) { + asm("mov %0, %%dr7" :: "r"(value)); +} + +static enum breakpoint_result allocate_breakpoint(int *out_handle) { + for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) { + if (allocated_breakpoints[i]) + continue; + + allocated_breakpoints[i] = 1; + handlers[i] = NULL; + *out_handle = i; + return BREAKPOINT_RES_OK; + } + + return BREAKPOINT_RES_NONE_AVAILABLE; +} + +static enum breakpoint_result validate_handle(int handle) { + if (handle < 0 || handle >= DEBUG_REGISTER_COUNT || + !allocated_breakpoints[handle]) { + return BREAKPOINT_RES_INVALID_HANDLE; + } + + return BREAKPOINT_RES_OK; +} + +enum breakpoint_result breakpoint_create_instruction(int *out_handle, void *virt_addr) { + enum breakpoint_result res = allocate_breakpoint(out_handle); + if (res != BREAKPOINT_RES_OK) { + return res; + } + + debug_write_addr_reg(*out_handle, (uintptr_t)virt_addr); + uintptr_t control = debug_read_control(); + control &= ~DEBUG_CTRL_LT_MASK(*out_handle); + control |= DEBUG_CTRL_LT(*out_handle, DEBUG_CTRL_LEN_1, DEBUG_CTRL_INSTR); + debug_write_control(control); + return BREAKPOINT_RES_OK; +} + +enum breakpoint_result breakpoint_create_data(int *out_handle, void *virt_addr, size_t len, bool write_only) { + uintptr_t len_value = 0; + switch (len) { + case 1: + len_value = DEBUG_CTRL_LEN_1; + break; + + case 2: + len_value = DEBUG_CTRL_LEN_2; + break; + + case 4: + len_value = DEBUG_CTRL_LEN_4; + break; + +#if ENV_X86_64 + /* Only supported on 64-bit CPUs */ + case 8: + len_value = DEBUG_CTRL_LEN_8; + break; +#endif + + default: + return BREAKPOINT_RES_INVALID_LENGTH; + + } + + enum breakpoint_result res = allocate_breakpoint(out_handle); + if (res != BREAKPOINT_RES_OK) { + return res; + } + + uintptr_t type = write_only ? DEBUG_CTRL_WRITE : DEBUG_CTRL_RW; + debug_write_addr_reg(*out_handle, (uintptr_t)virt_addr); + uintptr_t control = debug_read_control(); + control &= ~DEBUG_CTRL_LT_MASK(*out_handle); + control |= DEBUG_CTRL_LT(*out_handle, len_value, type); + debug_write_control(control); + return BREAKPOINT_RES_OK; +} + +enum breakpoint_result breakpoint_remove(int handle) { + enum breakpoint_result res = validate_handle(handle); + if (res != BREAKPOINT_RES_OK) { + return res; + } + breakpoint_enable(handle, 0); + + allocated_breakpoints[handle] = 0; + handlers[handle] = NULL; + return BREAKPOINT_RES_OK; +} + +enum breakpoint_result breakpoint_enable(int handle, bool enabled) { + enum breakpoint_result res = validate_handle(handle); + if (res != BREAKPOINT_RES_OK) { + return res; + } + + uintptr_t control = debug_read_control(); + control &= ~DEBUG_CTRL_ENABLE_MASK(handle); + if (enabled) { + control |= DEBUG_CTRL_ENABLE(handle, DEBUG_CTRL_ENABLE_GLOBAL); + } + debug_write_control(control); + return BREAKPOINT_RES_OK; +} + +enum breakpoint_result breakpoint_get_type(int handle, enum breakpoint_type* type) { + enum breakpoint_result res = validate_handle(handle); + if (res != BREAKPOINT_RES_OK) { + return res; + } + + *type = DEBUG_CTRL_GET_TYPE(handle, debug_read_control()); + return BREAKPOINT_RES_OK; +} + +enum breakpoint_result breakpoint_set_handler(int handle, breakpoint_handler handler) { + enum breakpoint_result res = validate_handle(handle); + if (res != BREAKPOINT_RES_OK) { + return res; + } + + handlers[handle] = handler; + return BREAKPOINT_RES_OK; +} + +int breakpoint_dispatch_handler(struct eregs* info) { + /* See which breakpoint was hit */ + uintptr_t status = debug_read_status(); + int bp = -1; + for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) { + if (DEBUG_STATUS_GET_BP_HIT(i, status)) { + bp = i; + break; + } + } + + if (bp == -1) { + return 0; + } + + /* Clear hit breakpoints */ + for (int i = 0; i < DEBUG_REGISTER_COUNT; i++) { + status &= ~DEBUG_STATUS_BP_HIT_MASK(i); + } + + debug_write_status(status); + + /* Call the breakpoint handler */ + int ret = 0; + if (handlers[bp]) { + ret = handlers[bp](bp, info); + } + + /* Default to instruction breakpoint so that if breakpoint_get_type fails, + for whatever reason, any instruction breakpoints won't get stuck. */ + enum breakpoint_type type = BREAKPOINT_TYPE_INSTRUCTION; + breakpoint_get_type(bp, &type); + + if (type == BREAKPOINT_TYPE_INSTRUCTION && ret == 0) { + /* Set the resume flag so the same breakpoint won't be hit again immediately. + Only need to set this if we won't be halting. */ +#if ENV_X86_64 + info->rflags |= FLAGS_RESUME; +#else + info->eflags |= FLAGS_RESUME; +#endif + } + + return ret; +} \ No newline at end of file diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c index 624226e3..1bffef4 100644 --- a/src/arch/x86/exception.c +++ b/src/arch/x86/exception.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/cpu.h> +#include <arch/breakpoint.h> +#include <arch/null_breakpoint.h> #include <arch/exception.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -371,8 +373,6 @@ } #endif /* CONFIG_GDB_STUB */ -#include <arch/registers.h> - void x86_exception(struct eregs *info); void x86_exception(struct eregs *info) @@ -488,6 +488,14 @@ int logical_processor = 0; u32 apic_id = CONFIG(SMP) ? lapicid() : 0; +#if ENV_RAMSTAGE && CONFIG_DEBUG_HW_BREAKPOINTS + if (info->vector == 1) { + if (breakpoint_dispatch_handler(info) == 0) { + return; + } + } +#endif + #if ENV_RAMSTAGE logical_processor = cpu_index(); #endif @@ -657,4 +665,8 @@ } load_idt(idt, sizeof(idt)); + +#if ENV_RAMSTAGE && CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS + null_breakpoint_init(); +#endif } diff --git a/src/arch/x86/include/arch/breakpoint.h b/src/arch/x86/include/arch/breakpoint.h new file mode 100644 index 0000000..8a47f98 --- /dev/null +++ b/src/arch/x86/include/arch/breakpoint.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _BREAKPOINT_H_ +#define _BREAKPOINT_H_ + +#ifdef CONFIG_DEBUG_HW_BREAKPOINTS + +#include <arch/registers.h> +#include <types.h> + +typedef int(*breakpoint_handler)(int, struct eregs *info); + +enum breakpoint_result { + BREAKPOINT_RES_OK = 0, + BREAKPOINT_RES_NONE_AVAILABLE = -1, + BREAKPOINT_RES_INVALID_HANDLE = -2, + BREAKPOINT_RES_INVALID_LENGTH = -3 +}; + +enum breakpoint_type { + BREAKPOINT_TYPE_INSTRUCTION, + BREAKPOINT_TYPE_DATA, + BREAKPOINT_TYPE_IO, +}; + +/* Creates an instruction breakpoint at the given address. */ +enum breakpoint_result breakpoint_create_instruction(int *out_handle, void *virt_addr); +/* Creates a data breakpoint at the given address for len bytes. */ +enum breakpoint_result breakpoint_create_data(int *out_handle, void *virt_addr, size_t len, bool write_only); +/* Removes a given breakpoint. */ +enum breakpoint_result breakpoint_remove(int handle); +/* Enables or disables a given breakpoint. */ +enum breakpoint_result breakpoint_enable(int handle, bool enabled); +/* Returns the type of a breakpoint. */ +enum breakpoint_result breakpoint_get_type(int handle, enum breakpoint_type* type); +/* + * Sets a handler function to be called when the breakpoint is hit. The handler should return 0 to continue + * or any other value to halt execution as a fatal error. + */ +enum breakpoint_result breakpoint_set_handler(int handle, breakpoint_handler handler); +/* Called by x86_exception to dispatch breakpoint exceptions to the correct handler. */ +int breakpoint_dispatch_handler(struct eregs *info); +#endif /* CONFIG_DEBUG_HW_BREAKPOINTS */ +#endif /* _BREAKPOINT_H_ */ \ No newline at end of file diff --git a/src/arch/x86/include/arch/null_breakpoint.h b/src/arch/x86/include/arch/null_breakpoint.h new file mode 100644 index 0000000..512a342 --- /dev/null +++ b/src/arch/x86/include/arch/null_breakpoint.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _NULL_BREAKPOINT_H_ +#define _NULL_BREAKPOINT_H_ + +#ifdef CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS + +/* Places data and instructions breakpoints at address zero. */ +void null_breakpoint_init(void); +#endif /* CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS */ +#endif /* _NULL_BREAKPOINT_H_ */ \ No newline at end of file diff --git a/src/arch/x86/null_breakpoint.c b/src/arch/x86/null_breakpoint.c new file mode 100644 index 0000000..19b6d6a --- /dev/null +++ b/src/arch/x86/null_breakpoint.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/breakpoint.h> +#include <arch/null_breakpoint.h> +#include <console/console.h> +#include <stdint.h> + +static int null_deref_bp = 0; +static int null_exec_bp = 0; + +static int handle_breakpoint(int handle, struct eregs* regs) +{ + if (handle == null_exec_bp) { + printk(BIOS_ERR, "Null instruction execution\n"); + } + else { +#if ENV_X86_64 + printk(BIOS_ERR, "Null dereference at rip: 0x%lx \n", regs->rip); +#else + printk(BIOS_ERR, "Null dereference at eip: 0x%x \n", regs->eip); +#endif + } + + return CONFIG_DEBUG_NULL_DEREF_HALT; +} + +void null_breakpoint_init(void) +{ + enum breakpoint_result res = breakpoint_create_data(&null_deref_bp, NULL, sizeof(uintptr_t), 0); + if (res != BREAKPOINT_RES_OK) { + printk(BIOS_ERR, "Failed to create NULL dereference breakpoint\n"); + } + + res = breakpoint_create_instruction(&null_exec_bp, NULL); + if (res != BREAKPOINT_RES_OK) { + printk(BIOS_ERR, "Failed to create NULL execution breakpoint\n"); + } + + breakpoint_set_handler(null_deref_bp, &handle_breakpoint); + breakpoint_set_handler(null_exec_bp, &handle_breakpoint); + + breakpoint_enable(null_deref_bp, 1); + breakpoint_enable(null_exec_bp, 1); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/63657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I113590689046a13c2a552741bbfe7668a834354a Gerrit-Change-Number: 63657 Gerrit-PatchSet: 1 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Allow for the tool to support additional PSP entries.
by Al Hirani (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Bao Zheng, Jason Nien, Paul Menzel. Al Hirani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62911 ) Change subject: amdfwtool: Allow for the tool to support additional PSP entries. ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62911/comment/e81a6f65_9730264a PS2, Line 8: > What PSP entries are not supported right now? Please start with a description of the problem. The tool has a limit to the number of PSP entries it can take as an input, so I can't specify which PSP entries because that's up to the user of the tool. https://review.coreboot.org/c/coreboot/+/62911/comment/45c42e91_1580444e PS2, Line 9: Consolidate the MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file > Please wrap lines after 72 characters, and add a dot/period to the end of sentences. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Gerrit-Change-Number: 62911 Gerrit-PatchSet: 3 Gerrit-Owner: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 15 Apr 2022 16:48:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool: Allow for the tool to support additional PSP entries.
by Al Hirani (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Bao Zheng, Jason Nien, Al Hirani. Hello Bao Zheng, build bot (Jenkins), ritul guru, Jason Nien, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62911 to look at the new patch set (#3). Change subject: amdfwtool: Allow for the tool to support additional PSP entries. ...................................................................... amdfwtool: Allow for the tool to support additional PSP entries. Consolidate the MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one file. Signed-off-by: Altamshali Hirani <al.hirani(a)amd.corp-partner.google.com> Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/62911/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d Gerrit-Change-Number: 62911 Gerrit-PatchSet: 3 Gerrit-Owner: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), Nico Huber, Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63639 to look at the new patch set (#4). Change subject: Add SBOM (Software Bill of Materials) Generation ...................................................................... Add SBOM (Software Bill of Materials) Generation Add Makefile.inc to Generate and build coswid tags Add templates for most payloads, coreboot and intel-microcode Add Kconfig entries to optionaly add coswid tags for payloads, coreboot and intel microcode Add CBFS entry called sbom to each build via Makefile.inc Motivation: https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materi… Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 --- M Makefile.inc M payloads/Kconfig M src/Kconfig A src/sbom/Makefile.inc A src/sbom/coreboot.ini.src A src/sbom/intel-microcode.ini.src A src/sbom/payload-BOOTBOOT.ini.src A src/sbom/payload-FILO.ini.src A src/sbom/payload-GRUB2.ini.src A src/sbom/payload-LinuxBoot.ini.src A src/sbom/payload-SeaBIOS.ini.src A src/sbom/payload-U-Boot.ini.src A src/sbom/payload-Yabits.ini.src A src/sbom/payload-depthcharge.ini.src A src/sbom/payload-iPXE.ini.src A src/sbom/payload-skiboot.ini.src M src/southbridge/intel/common/firmware/Kconfig 17 files changed, 326 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63639/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Gerrit-Change-Number: 63639 Gerrit-PatchSet: 4 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add SBOM (Software Bill of Materials) Generation
by Maximilian Brune (Code Review) 15 Apr '22

15 Apr '22

Attention is currently required from: Martin L Roth, Maximilian Brune. Hello build bot (Jenkins), Nico Huber, Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63639 to look at the new patch set (#3). Change subject: Add SBOM (Software Bill of Materials) Generation ...................................................................... Add SBOM (Software Bill of Materials) Generation Add Makefile.inc to Generate and build coswid tags Add templates for most payloads, coreboot and intel-microcode Add Kconfig entries to optionaly add coswid tags for payloads, coreboot and intel microcode Add CBFS entry called sbom to each build via Makefile.inc Motivation: https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materi… Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 --- M Makefile.inc M payloads/Kconfig M src/Kconfig A src/sbom/Makefile.inc A src/sbom/coreboot.ini.src A src/sbom/intel-microcode.ini.src A src/sbom/payload-BOOTBOOT.ini.src A src/sbom/payload-FILO.ini.src A src/sbom/payload-GRUB2.ini.src A src/sbom/payload-LinuxBoot.ini.src A src/sbom/payload-SeaBIOS.ini.src A src/sbom/payload-U-Boot.ini.src A src/sbom/payload-Yabits.ini.src A src/sbom/payload-depthcharge.ini.src A src/sbom/payload-iPXE.ini.src A src/sbom/payload-skiboot.ini.src M src/southbridge/intel/common/firmware/Kconfig 17 files changed, 326 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63639/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0 Gerrit-Change-Number: 63639 Gerrit-PatchSet: 3 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/msi/ms7d25: Configure PCIe Root Ports
by Michał Żygowski (Code Review) 15 Apr '22

15 Apr '22

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63656 ) Change subject: mb/msi/ms7d25: Configure PCIe Root Ports ...................................................................... mb/msi/ms7d25: Configure PCIe Root Ports Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f --- M src/mainboard/msi/ms7d25/devicetree.cb M src/mainboard/msi/ms7d25/romstage_fsp_params.c 2 files changed, 206 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/63656/1 diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 21e7625..b46bbab 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -79,8 +79,46 @@ [DDI_PORT_4] = DDI_ENABLE_HPD, }" + register "hybrid_storage_mode" = "1" + + register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[3]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[4]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[5]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[6]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[7]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[8]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[9]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[10]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[11]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[12]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[13]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[14]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[16]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[17]" = "PCIE_CLK_FREE_RUNNING" + device domain 0 on + device ref pcie5_0 on + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + .PcieRpL1Substates = L1_SS_DISABLED, + .pcie_rp_aspm = ASPM_DISABLE, + }" + smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" + "PCI_E1" "SlotDataBusWidth16X" + end device ref igpu on end + device ref pcie4_0 on + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + .PcieRpL1Substates = L1_SS_DISABLED, + .pcie_rp_aspm = ASPM_DISABLE, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_1" "SlotDataBusWidth4X" + end device ref crashlog off end device ref xhci on end device ref cnvi_wifi on end @@ -91,6 +129,171 @@ device ref heci3 off end device ref heci4 off end device ref sata on end + + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" + "PCI_E2" "SlotDataBusWidth1X" + end + device ref pcie_rp2 on + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" + "PCI_E4" "SlotDataBusWidth1X" + end + device ref pcie_rp3 on + # i225 Ethernet + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp4 off end + + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" + "PCI_E3" "SlotDataBusWidth4X" + end + device ref pcie_rp6 on + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp8 on + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_3" "SlotDataBusWidth4X" + end + device ref pcie_rp10 on + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp11 on + register "pch_pcie_rp[PCH_RP(11)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp12 on + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + + # These are not enabled. The Flex I/O mode is SATA to cover all 8 SATA ports. + # There is an ASMedia switch on-baord to mux the SATA ports 7, 8 and PCIe + # 9-12, 21-24 to M2_3 and M2_4 slots + device ref pcie_rp13 off end + device ref pcie_rp14 off end + device ref pcie_rp15 off end + device ref pcie_rp16 off end + device ref pcie_rp17 off end + device ref pcie_rp18 off end + device ref pcie_rp19 off end + device ref pcie_rp20 off end + + device ref pcie_rp21 on + register "pch_pcie_rp[PCH_RP(21)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_4" "SlotDataBusWidth4X" + end + device ref pcie_rp22 on + register "pch_pcie_rp[PCH_RP(22)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp23 on + register "pch_pcie_rp[PCH_RP(23)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp24 on + register "pch_pcie_rp[PCH_RP(24)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + + device ref pcie_rp25 on + register "pch_pcie_rp[PCH_RP(25)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M2_2" "SlotDataBusWidth4X" + end + device ref pcie_rp26 on + register "pch_pcie_rp[PCH_RP(26)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp27 on + register "pch_pcie_rp[PCH_RP(27)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref pcie_rp28 on + register "pch_pcie_rp[PCH_RP(28)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED | PCIE_RP_LTR | PCIE_RP_AER, + .PcieRpL1Substates = L1_SS_L1_2, + .pcie_rp_aspm = ASPM_L0S_L1, + }" + end + device ref p2sb on end device ref hda on end device ref smbus on end diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index e6b8515..c45950f 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -51,6 +51,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { memupd->FspmConfig.FirstDimmBitMask = 0xA; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50199d2caf54509a72c5100acb770bf766327e7f Gerrit-Change-Number: 63656 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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