coreboot-gerrit April 2022

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Change in coreboot[master]: nb/intel/snb: Reduce scope of functions
by Arthur Heymans (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Angel Pons. Hello Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63701 to look at the new patch set (#2). Change subject: nb/intel/snb: Reduce scope of functions ...................................................................... nb/intel/snb: Reduce scope of functions Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/raminit.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 5 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/63701/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Gerrit-Change-Number: 63701 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/snb: Reduce scope of function
by Arthur Heymans (Code Review) 18 Apr '22

18 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63701 ) Change subject: nb/intel/snb: Reduce scope of function ...................................................................... nb/intel/snb: Reduce scope of function Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/raminit.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/63701/1 diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index dd4e572..c5d881a 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -13,6 +13,5 @@ void save_mrc_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); -void setup_sdram_meminfo(struct pei_data *pei_data); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index fbb2b6e..ff7f1ed 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -320,6 +320,8 @@ RCBA32(FD) |= PCH_DISABLE_P2P; } +static void setup_sdram_meminfo(struct pei_data *pei_data); + void perform_raminit(int s3resume) { struct pei_data pei_data; @@ -390,7 +392,7 @@ setup_sdram_meminfo(&pei_data); } -void setup_sdram_meminfo(struct pei_data *pei_data) +static void setup_sdram_meminfo(struct pei_data *pei_data) { u32 addr_decoder_common, addr_decode_ch[2]; struct memory_info *mem_info; -- To view, visit https://review.coreboot.org/c/coreboot/+/63701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idefbe15c5f7c7169d9b60079b90cd02affb261ca Gerrit-Change-Number: 63701 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Michał Kopeć (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Paul Menzel, Angel Pons, Michael Niewöhner, Piotr Król, Felix Held. Michał Kopeć has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63672 ) Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... Patch Set 2: (8 comments) Commit Message: PS1: > Please wrap lines at 72 characters. For the commit summary, try to abbreviate it a bit. Fixed line wrapping and split the changes into 2 sommits, so this commit message is not as long anymore https://review.coreboot.org/c/coreboot/+/63672/comment/806cf913_9776d803 PS1, Line 14: Additionally, decouple temperature offset/min/max configuration from TMPIN : mode configuration, since in these SIOs, TMPINs do not have to map directly : to temperature reading registers (e.g. TMPIN1 can read to temperature reading : register 3). > +1, this can and should be done in two commits: […] Moved TMPIN/temp config decoupling to CB:63700 https://review.coreboot.org/c/coreboot/+/63672/comment/d1a8c018_fd9fd126 PS1, Line 19: Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs. > Is there no way to determin the number of registers at run-time? I don't know of a way to determine this, but as Angel says, it's known at build time anyway Patchset: PS2: Moved the TMPIN / temperature reg config split to CB:63700 File src/superio/ite/common/env_ctrl.c: https://review.coreboot.org/c/coreboot/+/63672/comment/f286766e_e68c1e21 PS1, Line 125: int > bool? Done https://review.coreboot.org/c/coreboot/+/63672/comment/74f3d0c4_601ec8ff PS1, Line 127: if (source >= THERMAL_SOURCE_PECI1 && source <= THERMAL_SOURCE_PECI5) : return 1; : : return 0; > Something like: […] Yes... done. https://review.coreboot.org/c/coreboot/+/63672/comment/ab26471c_a07f12ab PS1, Line 138: > nit: drop blank line Done https://review.coreboot.org/c/coreboot/+/63672/comment/3d635d53_12e597c8 PS1, Line 145: temp - 1 > Looks like you could refactor this to avoid the `- 1` everywhere. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Apr 2022 15:09:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Michał Kopeć (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Paul Menzel, Michael Niewöhner, Piotr Król, Felix Held. Hello build bot (Jenkins), Damien Zammit, Michał Żygowski, Paul Menzel, Angel Pons, Michael Niewöhner, Piotr Król, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63672 to look at the new patch set (#3). Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... superio/ite/common: Add support for SuperIOs with 6 temperature reading registers Some ITE SuperIOs such as IT8613E or IT8625E have 6 temperature reading registers, to which values can be read from any TMPINs or external sources. These SuperIOs have Temperature Source Select registers in bank 2 of EC space. Enable thermal monitoring on these SIOs by programming these registers. Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs. Based on IT8613E "Preliminary Specification V0.3 (For E Version)" and IT8625E "Preliminary Specification V0.3 (For D Version)" Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/it8613e/Kconfig 5 files changed, 78 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63672/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: superio/ite/common: Decouple TMPIN from thermal config
by Michał Kopeć (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Piotr Król, Felix Held. Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63700 ) Change subject: superio/ite/common: Decouple TMPIN from thermal config ...................................................................... superio/ite/common: Decouple TMPIN from thermal config Some ITE SuperIOs can read any internal or external temperature sources to any temperature reading registers. Therefore, decouple TMPINn mode config from thermal offset/range config. Change-Id: I9650a26d79c325fd629adb24a8d897fd62e5f0a5 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/mainboard/acer/g43t-am3/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl_chip.h 7 files changed, 46 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/63700/1 diff --git a/src/mainboard/acer/g43t-am3/devicetree.cb b/src/mainboard/acer/g43t-am3/devicetree.cb index a713f34..f8d426d1 100644 --- a/src/mainboard/acer/g43t-am3/devicetree.cb +++ b/src/mainboard/acer/g43t-am3/devicetree.cb @@ -54,9 +54,9 @@ register "TMPIN1.mode" = "THERMAL_DIODE" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_PECI" - register "TMPIN3.offset" = "100" - register "TMPIN3.min" = "0" - register "TMPIN3.max" = "100" + register "TEMP3.offset" = "100" + register "TEMP3.min" = "0" + register "TEMP3.max" = "100" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" # CPU fan register "FAN1.smart.tmpin" = "3" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..d9eb149 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -53,7 +53,7 @@ device pci 1f.0 on # ISA bridge chip superio/ite/it8720f # Super I/O register "TMPIN1.mode" = "THERMAL_DIODE" - register "TMPIN1.offset" = "0" + register "TEMP1.offset" = "0" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..6880b85 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -102,7 +102,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN_ALL" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d7ddf9e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -72,7 +72,7 @@ register "TMPIN1.mode" = "THERMAL_RESISTOR" register "TMPIN2.mode" = "THERMAL_RESISTOR" register "TMPIN3.mode" = "THERMAL_DIODE" - register "TMPIN3.offset" = "0" + register "TEMP3.offset" = "0" register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 39c2e33..d4bbbac 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -194,10 +194,10 @@ end chip superio/ite/it8786e register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "100" - register "TMPIN1.min" = "128" + register "TEMP1.offset" = "100" + register "TEMP1.min" = "128" register "TMPIN2.mode" = "THERMAL_RESISTOR" - register "TMPIN2.min" = "128" + register "TEMP2.min" = "128" register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" register "ec.vin_mask" = "VIN_ALL" # FAN1 is CPU fan (on board) diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9149c58..f329935 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -58,7 +58,7 @@ * into TMPINx register */ static void enable_tmpin(const u16 base, const u8 tmpin, - const struct ite_ec_thermal_config *const conf) + const struct ite_ec_tmpin_config *const conf) { u8 reg; u8 reg_extra; @@ -109,19 +109,26 @@ } pnp_write_hwm5_index(base, ITE_EC_ADC_TEMP_CHANNEL_ENABLE, reg); +} + +/* + * Configure temperature reading registers (offsets, limits) + */ +static void enable_temp(const u16 base, const u8 temp, + const struct ite_ec_thermal_config *const conf) +{ + u8 reg; /* Set temperature offsets */ - if (conf->mode != THERMAL_RESISTOR) { - reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); - reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; - pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); - pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[tmpin-1], conf->offset); - } + reg = pnp_read_hwm5_index(base, ITE_EC_BEEP_ENABLE); + reg |= ITE_EC_TEMP_ADJUST_WRITE_ENABLE; + pnp_write_hwm5_index(base, ITE_EC_BEEP_ENABLE, reg); + pnp_write_hwm5_index(base, ITE_EC_TEMP_ADJUST[temp], conf->offset); /* Set temperature limits */ u8 max = conf->max; - pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(tmpin), max ? max : 127); - pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(tmpin), conf->min); + pnp_write_hwm5_index(base, ITE_EC_HIGH_TEMP_LIMIT(temp), max ? max : 127); + pnp_write_hwm5_index(base, ITE_EC_LOW_TEMP_LIMIT(temp), conf->min); /* Enable the startup of monitoring operation */ reg = pnp_read_hwm5_index(base, ITE_EC_CONFIGURATION); @@ -286,6 +293,10 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Configure temperature reading registers */ + for (i = 0; i < ITE_EC_TEMP_CNT; ++i) + enable_temp(base, i, &conf->temp[i]); + /* Enable External Sensor SMBus Host if configured */ if (conf->smbus_en) { pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 2bb0780..947df57 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -5,6 +5,8 @@ #define ITE_EC_TMPIN_CNT 3 +#define ITE_EC_TEMP_CNT 3 + #if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CNT 5 #else @@ -12,15 +14,18 @@ #endif /* Supported thermal mode on TMPINx */ -enum ite_ec_thermal_mode { +enum ite_ec_tmpin_mode { THERMAL_MODE_DISABLED = 0, THERMAL_DIODE, THERMAL_RESISTOR, THERMAL_PECI, }; +struct ite_ec_tmpin_config { + enum ite_ec_tmpin_mode mode; +}; + struct ite_ec_thermal_config { - enum ite_ec_thermal_mode mode; /* Offset is used for diode sensors and PECI */ u8 offset; /* Limits */ @@ -78,7 +83,12 @@ /* * Enable temperature sensors in given mode. */ - struct ite_ec_thermal_config tmpin[ITE_EC_TMPIN_CNT]; + struct ite_ec_tmpin_config tmpin[ITE_EC_TMPIN_CNT]; + + /* + * Configure temperature reading registers. + */ + struct ite_ec_thermal_config temp[ITE_EC_TEMP_CNT]; /* * Enable a FAN in given mode. @@ -105,6 +115,10 @@ #define TMPIN2 ec.tmpin[1] #define TMPIN3 ec.tmpin[2] +#define TEMP1 ec.temp[0] +#define TEMP2 ec.temp[1] +#define TEMP3 ec.temp[2] + #define FAN1 ec.fan[0] #define FAN2 ec.fan[1] #define FAN3 ec.fan[2] -- To view, visit https://review.coreboot.org/c/coreboot/+/63700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9650a26d79c325fd629adb24a8d897fd62e5f0a5 Gerrit-Change-Number: 63700 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/ite/common: Add support for SuperIOs with 6 temperature readi...
by Michał Kopeć (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Damien Zammit, Michał Żygowski, Paul Menzel, Michał Kopeć, Michael Niewöhner, Piotr Król, Felix Held. Hello build bot (Jenkins), Damien Zammit, Michał Żygowski, Paul Menzel, Angel Pons, Michael Niewöhner, Piotr Król, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63672 to look at the new patch set (#2). Change subject: superio/ite/common: Add support for SuperIOs with 6 temperature reading registers ...................................................................... superio/ite/common: Add support for SuperIOs with 6 temperature reading registers Some ITE SuperIOs such as IT8613E or IT8625E have 6 temperature reading registers, to which values can be read from any TMPINs or external sources. These SuperIOs have Temperature Source Select registers in bank 2 of EC space. Enable thermal monitoring on these SIOs by programming these registers. Add a Kconfig option SUPERIO_ITE_ENV_CTRL_6_TEMPS for these ECs. Based on IT8613E "Preliminary Specification V0.3 (For E Version)" and IT8625E "Preliminary Specification V0.3 (For D Version)" Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h M src/superio/ite/it8613e/Kconfig 5 files changed, 76 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63672/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63672 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea7be22e4d1c8e56683755bff7fbb54e9218734e Gerrit-Change-Number: 63672 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Update APU STT setting
by Chris Wang (Code Review) 18 Apr '22

18 Apr '22

Chris Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63699 ) Change subject: mb/google/guybrush/var/dewatt: Update APU STT setting ...................................................................... mb/google/guybrush/var/dewatt: Update APU STT setting update STT setting for dewatt. BUG=b:228040295 BRANCH=guybrush TEST=build, verify the parameter has been applied to the system by checking the AGT tool. Signed-off-by: Chris.Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af --- M src/mainboard/google/guybrush/variants/dewatt/overridetree.cb 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/63699/1 diff --git a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb index 866aee5..84bf9da 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/dewatt/overridetree.cb @@ -27,6 +27,28 @@ register "telemetry_vddcrsocfull_scale_current_mA" = "29785" #mA register "telemetry_vddcrsocoffset" = "461" + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "15000" + register "stt_m1" = "0x022B" + register "stt_m2" = "0x117" + register "stt_m3" = "0" + register "stt_m4" = "0" + register "stt_m5" = "0" + register "stt_m6" = "0" + register "stt_c_apu" = "0xBA4" + register "stt_c_gpu" = "0" + register "stt_c_hs2" = "0" + register "stt_alpha_apu" = "0x199A" + register "stt_alpha_gpu" = "0" + register "stt_alpha_hs2" = "0" + register "stt_skin_temp_apu" = "0x2D00" + register "stt_skin_temp_gpu" = "0" + register "stt_skin_temp_hs2" = "0" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0x2666" + #USB 2/3 phy config register "usb_phy" = "{ /* Left USB C0 Port */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id319d42747dd0d5f6a9ca727635d85e6b9bd65af Gerrit-Change-Number: 63699 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Varshit B Pandya (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63697 ) Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/63697/comment/d999d166_fd0fb243 PS2, Line 377: acpigen_write_device("TPWR"); > one question is this belong to TPWR device? put it together? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 14:55:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Varshit B Pandya (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Varshit B Pandya, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar. Hello build bot (Jenkins), Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63697 to look at the new patch set (#3). Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... drivers/intel/dptf: Add support for PROP method Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of platform power in miliWatts. This value is static, which has to configured from devicetree of overridetree for each platform BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check PROP method Scope (\_SB) { Device (DPTF) { Device (TPWR) { Method (PROP, 0, Serialized) { Return (XXXX) } } } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 --- M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c 2 files changed, 30 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/63697/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPI fast speed
by Rob Barnes (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Kenneth Chan, Karthik Ramasubramanian. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63685 ) Change subject: mb/google/guybrush/var/dewatt: Override SPI fast speed ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Gerrit-Change-Number: 63685 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 14:21:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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