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Change subject: soc/intel/alderlake: Implement PCH lock down configuration
......................................................................
soc/intel/alderlake: Implement PCH lock down configuration
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
---
M src/soc/intel/alderlake/lockdown.c
1 file changed, 17 insertions(+), 0 deletions(-)
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Change subject: soc/intel/alderlake: Implement PMC soft strap interface lock
......................................................................
soc/intel/alderlake: Implement PMC soft strap interface lock
This patch implements API to perform locking of the PMC soft strap
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0x00000001
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d
---
M src/soc/intel/alderlake/lockdown.c
1 file changed, 10 insertions(+), 1 deletion(-)
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Change subject: drivers/intel/dptf: Add support for PROP method
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/intel/dptf/dptf.c:
https://review.coreboot.org/c/coreboot/+/63697/comment/f0b620a4_eeaea6cb
PS2, Line 377: acpigen_write_device("TPWR");
one question is this belong to TPWR device? put it together?
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Change subject: drivers/intel/dptf: Add support for PROP method
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63697/comment/e41a381d_a051ced5
PS1, Line 9: Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of
> Please check the alignment for the comment.
Done
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I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/dptf: Add support for PROP method
......................................................................
drivers/intel/dptf: Add support for PROP method
Add PROP method under \_SB.DPTF.TPWR scope which will return static
worst case rest of platform power in miliWatts.
This value is static, which has to configured from devicetree of
overridetree for each platform
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check PROP method
Scope (\_SB.DPTF.TPWR)
{
Method (PROP, 0, Serialized)
{
Return (XXXX)
}
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com>
Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759
---
M src/drivers/intel/dptf/chip.h
M src/drivers/intel/dptf/dptf.c
2 files changed, 18 insertions(+), 0 deletions(-)
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Change subject: crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0
......................................................................
crossgcc: Upgrade LLVM from 13.0.1 to 14.0.0
Also upgrade CMake from 3.23.0 to 3.23.1
Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M util/crossgcc/buildgcc
D util/crossgcc/sum/clang-13.0.1.src.tar.xz.cksum
A util/crossgcc/sum/clang-14.0.0.src.tar.xz.cksum
D util/crossgcc/sum/clang-tools-extra-13.0.1.src.tar.xz.cksum
A util/crossgcc/sum/clang-tools-extra-14.0.0.src.tar.xz.cksum
D util/crossgcc/sum/cmake-3.23.0.tar.gz.cksum
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D util/crossgcc/sum/compiler-rt-13.0.1.src.tar.xz.cksum
A util/crossgcc/sum/compiler-rt-14.0.0.src.tar.xz.cksum
D util/crossgcc/sum/llvm-13.0.1.src.tar.xz.cksum
A util/crossgcc/sum/llvm-14.0.0.src.tar.xz.cksum
11 files changed, 7 insertions(+), 7 deletions(-)
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Change subject: mb/google/brask/variants/moli: update overridetree
......................................................................
Patch Set 22:
(1 comment)
File src/mainboard/google/brya/variants/moli/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63080/comment/37817747_f97171ca
PS7, Line 8: option STORAGE_NVME 0
: option STORAGE_EMMC 1
> Hi Zhuohao, […]
Hi, Zhuohao
please review it, thanks.
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Change subject: drivers/intel/dptf: Add support for PROP method
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63697/comment/fc6b3754_99a5f180
PS1, Line 9: Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of
Please check the alignment for the comment.
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Change subject: mb/*/*/irq_tables.c: Use ALIGN_UP macro
......................................................................
mb/*/*/irq_tables.c: Use ALIGN_UP macro
Change-Id: I2bd5e09f51918fe4c7e954edf54ab4d9bc629fd1
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/mainboard/amd/gardenia/irq_tables.c
M src/mainboard/amd/inagua/irq_tables.c
M src/mainboard/amd/olivehill/irq_tables.c
M src/mainboard/amd/parmer/irq_tables.c
M src/mainboard/amd/persimmon/irq_tables.c
M src/mainboard/amd/south_station/irq_tables.c
M src/mainboard/amd/thatcher/irq_tables.c
M src/mainboard/amd/union_station/irq_tables.c
M src/mainboard/asrock/e350m1/irq_tables.c
M src/mainboard/asrock/imb-a180/irq_tables.c
M src/mainboard/asus/f2a85-m/irq_tables.c
M src/mainboard/bap/ode_e20XX/irq_tables.c
M src/mainboard/biostar/a68n_5200/irq_tables.c
M src/mainboard/elmex/pcm205400/irq_tables.c
M src/mainboard/gizmosphere/gizmo/irq_tables.c
M src/mainboard/gizmosphere/gizmo2/irq_tables.c
M src/mainboard/google/kahlee/irq_tables.c
M src/mainboard/hp/abm/irq_tables.c
M src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c
M src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
M src/mainboard/lenovo/g505s/irq_tables.c
M src/mainboard/lippert/frontrunner-af/irq_tables.c
M src/mainboard/msi/ms7721/irq_tables.c
M src/mainboard/pcengines/apu1/irq_tables.c
M src/mainboard/pcengines/apu2/irq_tables.c
25 files changed, 49 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61919/3
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Gerrit-MessageType: newpatchset