coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/skyrim: Unmask espi, debug keyboard
by Jon Murphy (Code Review) 18 Apr '22

18 Apr '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63704 ) Change subject: mb/google/skyrim: Unmask espi, debug keyboard ...................................................................... mb/google/skyrim: Unmask espi, debug keyboard Unmask espi interrupts, add keyboard init and debug BUG=b:227282870 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1 --- M src/mainboard/google/skyrim/bootblock.c M src/mainboard/google/skyrim/ec.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb 4 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/63704/1 diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c index 4128090..ddf1a63 100644 --- a/src/mainboard/google/skyrim/bootblock.c +++ b/src/mainboard/google/skyrim/bootblock.c @@ -10,6 +10,8 @@ size_t num_gpios; const struct soc_amd_gpio *gpios; + espi_disable_lpc_ldrq(); + variant_espi_gpio_table(&gpios, &num_gpios); gpio_configure_pads(gpios, num_gpios); diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c index bc29833..ab40e2b 100644 --- a/src/mainboard/google/skyrim/ec.c +++ b/src/mainboard/google/skyrim/ec.c @@ -11,7 +11,7 @@ static const struct sci_source espi_sci_sources[] = { { .scimap = SMITYPE_ESPI_SYS, - .gpe = GEVENT_3, + .gpe = EC_SCI_GPI, .direction = SMI_SCI_LVL_HIGH, /* enum smi_sci_lvl */ .level = SMI_SCI_EDG, /* enum smi_sci_dir */ } diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 7c89f49..103a833 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <baseboard/variants.h> #include <console/console.h> @@ -111,6 +112,13 @@ init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + /* Write SLAVE0_RXVW_MISC_CNTL to disable IRQ grouping */ + write32((void *)0xfec200a8, 0); + + /* TODO: b/184678786 - Move into espi_config */ + /* Unmask eSPI IRQ 1 (Keyboard) */ + pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index a6894ee..f0d1039 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -35,7 +35,7 @@ .oob_ch_en = 0, .flash_ch_en = 0, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), }" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | -- To view, visit https://review.coreboot.org/c/coreboot/+/63704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1 Gerrit-Change-Number: 63704 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/sabrina: Disable lpc ldrq function
by Jon Murphy (Code Review) 18 Apr '22

18 Apr '22

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63703 ) Change subject: soc/amd/sabrina: Disable lpc ldrq function ...................................................................... soc/amd/sabrina: Disable lpc ldrq function Add function to disable lpc ldrq for espi. BUG=b:227282870 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I680c10dc8916c23ce6934d87aee5e484d4a84b78 --- M src/soc/amd/sabrina/espi_util.c M src/soc/amd/sabrina/include/soc/espi.h 2 files changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/63703/1 diff --git a/src/soc/amd/sabrina/espi_util.c b/src/soc/amd/sabrina/espi_util.c index 20db1b6..bad0589 100644 --- a/src/soc/amd/sabrina/espi_util.c +++ b/src/soc/amd/sabrina/espi_util.c @@ -1,14 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> +#include <amdblocks/lpc.h> +#include <device/pci_ops.h> #include <amdblocks/spi.h> #include <soc/espi.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> #include <types.h> -#define ESPI_CNTRL_REGISTER 0x10 -#define LOCK_SPIX10_BIT2 BIT(3) -#define ESPI_MUX_SPI1 BIT(2) -#define ROM_ADDR_WR_PROT BIT(1) -#define DIS_ESPI_MASCTL_REG_WR BIT(0) +void espi_disable_lpc_ldrq(void) +{ + /* Beware that the bit definitions for LPC_LDRQ0_PU_EN and LPC_LDRQ0_PD_EN are swapped + on Picasso and older compared to Renoir/Cezanne and newer */ + uint32_t dword = pci_read_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS); + dword &= ~(LPC_LDRQ0_PU_EN | LPC_LDRQ1_EN | LPC_LDRQ0_EN); + dword |= LPC_LDRQ0_PD_EN; + pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword); +} void espi_switch_to_spi1_pads(void) { diff --git a/src/soc/amd/sabrina/include/soc/espi.h b/src/soc/amd/sabrina/include/soc/espi.h index 76af3a1..5631ede 100644 --- a/src/soc/amd/sabrina/include/soc/espi.h +++ b/src/soc/amd/sabrina/include/soc/espi.h @@ -3,6 +3,13 @@ #ifndef AMD_SABRINA_ESPI_H #define AMD_SABRINA_ESPI_H +#define ESPI_CNTRL_REGISTER 0x10 +#define LOCK_SPIX10_BIT2 BIT(3) +#define ESPI_MUX_SPI1 BIT(2) +#define ROM_ADDR_WR_PROT BIT(1) +#define DIS_ESPI_MASCTL_REG_WR BIT(0) + +void espi_disable_lpc_ldrq(void); void espi_switch_to_spi1_pads(void); #endif /* AMD_SABRINA_ESPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I680c10dc8916c23ce6934d87aee5e484d4a84b78 Gerrit-Change-Number: 63703 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: add lockdown mode detection
by Eloy (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63702 to look at the new patch set (#4). Change subject: util/inteltool: add lockdown mode detection ...................................................................... util/inteltool: add lockdown mode detection Fixes https://github.com/zamaudio/intelmetool/issues/20. When lockdown mode in the Linux kernel is active, it blocks privileged I/O operations. Make the error message less confusing when inteltool is run with root permissions. Change-Id: I9914fe392d53be390924e60dbfb16d3c9d222f44 Signed-off-by: Eloy Degen <degeneloy(a)gmail.com> --- M util/inteltool/inteltool.c 1 file changed, 49 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63702/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9914fe392d53be390924e60dbfb16d3c9d222f44 Gerrit-Change-Number: 63702 Gerrit-PatchSet: 4 Gerrit-Owner: Eloy Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/inteltool: add lockdown mode detection
by Eloy (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Eloy, Stefan Reinauer. Hello build bot (Jenkins), Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63702 to look at the new patch set (#3). Change subject: util/inteltool: add lockdown mode detection ...................................................................... util/inteltool: add lockdown mode detection This commit fixes https://github.com/zamaudio/intelmetool/issues/20, because lockdown mode in the kernel blocks privileged I/O operations. When lockdown mode is used, this commit makes the error message less confusing when inteltool is ran with root permissions Change-Id: I9914fe392d53be390924e60dbfb16d3c9d222f44 Signed-off-by: Eloy Degen <degeneloy(a)gmail.com> --- M util/inteltool/inteltool.c 1 file changed, 49 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63702/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9914fe392d53be390924e60dbfb16d3c9d222f44 Gerrit-Change-Number: 63702 Gerrit-PatchSet: 3 Gerrit-Owner: Eloy Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eloy Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers
by Tim Wawrzynczak (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Matt DeVillier. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63561 ) Change subject: drivers/i2c/dw_i2c: Adjust to handle 0-byte transfers ...................................................................... Patch Set 1: (1 comment) File src/drivers/i2c/designware/dw_i2c.c: https://review.coreboot.org/c/coreboot/+/63561/comment/f1200bda_e11138d9 PS1, Line 431: if (segments->len != 0) > I did that so that there weren't a bunch of spurious TX aborted msgs in cbmem. […] what about BIOS_INFO or SPEW? -- To view, visit https://review.coreboot.org/c/coreboot/+/63561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I518e849f4c476c264a1464886b1853af66c0b29d Gerrit-Change-Number: 63561 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 19:06:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add a workaround for cnvi
by Tim Wawrzynczak (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Jamie Chen, Subrata Banik, Tim Wawrzynczak, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 ) Change subject: soc/intel/jasperlake: Add a workaround for cnvi ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/intel/jasperlake/chip.h: https://review.coreboot.org/c/coreboot/+/63675/comment/4ba8a26c_2a915ea9 PS1, Line 424: /* : * This is a workaround to mitigate higher SoC power consumption in S0ix : * when the CNVI has background activity. : * : * This setting can only be enabled if xtalsdqdis (Bit 22) in cppmvric1 : * register is 1. : * 1: Enabled ; 0: Disabled : */ : bool cnvi_s0ix_wa; Can we also please mention - Setting this on a system that supports S0i3 (e.g. external bypass rails) will apparently break S0ix. - Affected Intel wireless chipsets - Tradeoff of fewer wakes vs. higher power -- To view, visit https://review.coreboot.org/c/coreboot/+/63675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Gerrit-Change-Number: 63675 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 19:00:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/inteltool: add lockdown mode detection
by Paul Menzel (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Eloy, Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63702 ) Change subject: util/inteltool: add lockdown mode detection ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63702/comment/68255bff_260319ec PS2, Line 8: Why should Intel tool display the lockdown mode? Please add a commit message body. File util/inteltool/inteltool.c: https://review.coreboot.org/c/coreboot/+/63702/comment/b42faf2c_50a2c9e9 PS2, Line 808: /* Check if kernel is in lockdown mode. : * Whether this part of sysfs is considered a : * stable kernel API part is unknown, since : * there is no explicit documentation : * stating so. There does not seems to be : * any other interface for checking wether the : * kernel is in lockdown mode. Until there is : * something better, parse the sysfs file. : * Because it is a sysfs file, fseek(3) or : * stat(2) are ineffective. You can only : * iterate until the state of the file : * handle is EOF, while it is copied into : * a buffer. Please reflow for at least 72 characters per line. -- To view, visit https://review.coreboot.org/c/coreboot/+/63702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9914fe392d53be390924e60dbfb16d3c9d222f44 Gerrit-Change-Number: 63702 Gerrit-PatchSet: 2 Gerrit-Owner: Eloy Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eloy Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Apr 2022 18:54:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: crota: enable boot from SSD/ eMMC
by Tim Wawrzynczak (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63683 ) Change subject: crota: enable boot from SSD/ eMMC ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63683/comment/9ce97930_7da9f6e9 PS4, Line 14: `boot` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Gerrit-Change-Number: 63683 Gerrit-PatchSet: 4 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 18:52:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: crota: limit dram speed at 4800
by Tim Wawrzynczak (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63682 ) Change subject: crota: limit dram speed at 4800 ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63682/comment/b6972e1f_02d45cbe PS1, Line 8: Can we add the reason why here? -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 18:50:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add LPDDR5 DRAM type
by Tim Wawrzynczak (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Subrata Banik, Scott Chao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63680 ) Change subject: lib: Add LPDDR5 DRAM type ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98ba9e87b1a093b93434334a75c9a9252effa933 Gerrit-Change-Number: 63680 Gerrit-PatchSet: 2 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 18:50:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022