coreboot-gerrit April 2022

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Varshit B Pandya (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63697 ) Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... Patch Set 1: (3 comments) Patchset: PS1: ACK, will add check in next patchset File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/63697/comment/0fc5002f_45aaa818 PS1, Line 518: acpigen_write_integer(config->prop); > Please add check if this is mandatory. Ack https://review.coreboot.org/c/coreboot/+/63697/comment/7bdd094d_52bfc22c PS1, Line 533: write_prop(config); > If this is no mandatory, please add check here to skip if value is 0. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 11:29:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Eric Lai (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Varshit B Pandya, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63697 ) Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... Patch Set 1: (2 comments) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/63697/comment/64caa402_b237d373 PS1, Line 518: acpigen_write_integer(config->prop); Please add check if this is mandatory. https://review.coreboot.org/c/coreboot/+/63697/comment/a531ac5f_7f458f6e PS1, Line 533: write_prop(config); If this is no mandatory, please add check here to skip if value is 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 11:27:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Configure PROP value for brya
by Varshit B Pandya (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63698 ) Change subject: mb/google/brya: Configure PROP value for brya ...................................................................... mb/google/brya: Configure PROP value for brya Confugure PROP value to 20000 mW for brya variants. BUG=b:205928013 TEST=Build, boot brya0, dump SSDT and PROP method with configured value Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Id39c1e7bf35b537fca0b97bfe77b2ae3c3cf4ecc --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/brya4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/63698/1 diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index fd8224c..7479b8e 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -147,6 +147,8 @@ register "options.fan.fine_grained_control" = "1" register "options.fan.step_size" = "2" + ## PROP in mW + register "prop" = "20000" device generic 0 alias dptf_policy on end end end diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb index af0f43e..3974c0e 100644 --- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb @@ -146,6 +146,8 @@ register "options.fan.fine_grained_control" = "1" register "options.fan.step_size" = "2" + ## PROP in mW + register "prop" = "20000" device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id39c1e7bf35b537fca0b97bfe77b2ae3c3cf4ecc Gerrit-Change-Number: 63698 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/dptf: Add support for PROP method
by Varshit B Pandya (Code Review) 18 Apr '22

18 Apr '22

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63697 ) Change subject: drivers/intel/dptf: Add support for PROP method ...................................................................... drivers/intel/dptf: Add support for PROP method Add PROP method under \_SB.DPTF.TPWR scope which will return static worst case rest of platform power in miliWatts. This value is static, which has to configured from devicetree of overridetree for each platform BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check PROP method Scope (\_SB.DPTF.TPWR) { Method (PROP, 0, Serialized) { Return (XXXX) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 --- M src/drivers/intel/dptf/chip.h M src/drivers/intel/dptf/dptf.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/63697/1 diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h index 59b1e25..060f196 100644 --- a/src/drivers/intel/dptf/chip.h +++ b/src/drivers/intel/dptf/chip.h @@ -59,6 +59,9 @@ struct { uint32_t oem_variables[DPTF_OEM_VARIABLE_COUNT]; } oem_data; + + /* Rest of platform Power */ + uint32_t prop; }; #endif /* _DRIVERS_INTEL_DPTF_CHIP_H_ */ diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c index 27c7133..f7980ef 100644 --- a/src/drivers/intel/dptf/dptf.c +++ b/src/drivers/intel/dptf/dptf.c @@ -508,6 +508,19 @@ } } +static void write_prop(const struct drivers_intel_dptf_config *config) +{ + /* Rest of Platform Power */ + dptf_write_scope(DPTF_POWER); + acpigen_write_method_serialized("PROP", 0); + + acpigen_emit_byte(RETURN_OP); + acpigen_write_integer(config->prop); + + acpigen_pop_len(); /* Method PROP */ + acpigen_pop_len(); /* DPTF_POWER scope */ +} + /* Add custom tables and methods to SSDT */ static void dptf_fill_ssdt(const struct device *dev) { @@ -517,6 +530,7 @@ write_policies(config); write_controls(config); write_options(config); + write_prop(config); printk(BIOS_INFO, DPTF_DEVICE_PATH ": %s at %s\n", dev->chip_ops->name, dev_path(dev)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1415d2a9eb55cfadc3a7b41b53ecbec657002759 Gerrit-Change-Number: 63697 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 ) Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63630/comment/3ba2096e_9e53deb5 PS3, Line 103: lpc_set_eiss > Ack CB:63687 -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 09:33:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marc Jones <marc(a)marcjonesconsulting.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration)
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63693 ) Change subject: soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration) ...................................................................... soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration) Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig to skip FSP notify API (Post PCI Enumeration) and make use of native coreboot driver to perform SoC recommended operations prior booting to payload/OS. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects required configs. [INFO ] coreboot skipped calling FSP notify phase: 00000020. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63693/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 35fd2f7..9bc0a46 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -117,7 +117,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING - select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM config ALDERLAKE_CONFIGURE_DESCRIPTOR bool -- To view, visit https://review.coreboot.org/c/coreboot/+/63693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4 Gerrit-Change-Number: 63693 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement PCH lock down configuration
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63692 ) Change subject: soc/intel/alderlake: Implement PCH lock down configuration ...................................................................... soc/intel/alderlake: Implement PCH lock down configuration This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c --- M src/soc/intel/alderlake/lockdown.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63692/1 diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index 4ee223e..bca48b0 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -8,14 +8,20 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> +#include <intelblocks/pcr.h> #include <intelblocks/pmc_ipc.h> #include <intelpch/lockdown.h> +#include <soc/pcr_ids.h> #include <soc/pm.h> #include <stdint.h> #define PMC_IPC_CPU_STRAP 0xB1 #define PMC_IPC_CPU_STRAP_LOCK 0 +/* Trap status Register */ +#define PCR_PSTH_CTRLREG 0x1d00 +#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -102,8 +108,19 @@ } } +static void pch_lockdown_cfg(void) +{ + if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + return; + + /* Enable IOSF Primary Trunk Clock Gating */ + pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); +} + void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + /* PCH lock down configuration */ + pch_lockdown_cfg(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c Gerrit-Change-Number: 63692 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63691 ) Change subject: soc/intel/alderlake: Implement PMC feature lock ...................................................................... soc/intel/alderlake: Implement PMC feature lock This patch locks PMC features like: debug mode configuration and host read access to PMC XRAM. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c --- M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/lockdown.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63691/1 diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index ca11ae9..07206cb 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -76,6 +76,10 @@ #define PRSTS 0x1810 +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) #define S3AC_GATE_SUS (1 << 0) diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index 3e05b0d..4ee223e 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -74,6 +74,17 @@ return; } +/* + * This function to lock PMC features like: + * debug mode configuration and host read access to PMC XRAM. + */ +static void pmc_feature_lock(void) +{ + void *pmcbase = pmc_mmio_regs(); + + setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | PM_CFG_XRAM_READ_DISABLE); +} + static void pmc_lockdown_cfg(int chipset_lockdown) { /* PMSYNC */ @@ -87,6 +98,7 @@ if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { pmc_st_pg_lock(); pmc_soft_strap_interface_lock(); + pmc_feature_lock(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Gerrit-Change-Number: 63691 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement PMC soft strap interface lock
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63690 ) Change subject: soc/intel/alderlake: Implement PMC soft strap interface lock ...................................................................... soc/intel/alderlake: Implement PMC soft strap interface lock This patch implements API to perform locking of the PMC soft strap interface using CPU Strap IPC command. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d --- M src/soc/intel/alderlake/lockdown.c 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/63690/1 diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index f7b2f3c..3e05b0d 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -8,10 +8,14 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> +#include <intelblocks/pmc_ipc.h> #include <intelpch/lockdown.h> #include <soc/pm.h> #include <stdint.h> +#define PMC_IPC_CPU_STRAP 0xB1 +#define PMC_IPC_CPU_STRAP_LOCK 0 + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -55,6 +59,21 @@ setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); } +static void pmc_soft_strap_interface_lock(void) +{ + struct pmc_ipc_buffer req = { 0 }; + struct pmc_ipc_buffer rsp; + uint32_t cmd; + + cmd = pmc_make_ipc_cmd(PMC_IPC_CPU_STRAP, PMC_IPC_CPU_STRAP_LOCK, 0); + if (pmc_send_ipc_cmd(cmd, &req, &rsp) != CB_SUCCESS) { + printk(BIOS_ERR, "PMC: Failed to lock Soft Strap Interface\n"); + return; + } + + return; +} + static void pmc_lockdown_cfg(int chipset_lockdown) { /* PMSYNC */ @@ -65,8 +84,10 @@ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); - if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { pmc_st_pg_lock(); + pmc_soft_strap_interface_lock(); + } } void soc_lockdown_config(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/63690 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d Gerrit-Change-Number: 63690 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement PMC static function lock
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63689 ) Change subject: soc/intel/alderlake: Implement PMC static function lock ...................................................................... soc/intel/alderlake: Implement PMC static function lock This patch implements API to perform static function lockdown and call `pmc_st_pg_lock()` from `pmc_lockdown_cfg()`. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified PMC static PG lock (bit 31) is set. > iotools mmio_read32 0xfe001e20 0x80000000 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60 --- M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/lockdown.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/63689/1 diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index 52cc0b5..ca11ae9 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -142,6 +142,9 @@ #define ACPI_EN (1 << 7) #define SCI_IRQ_SEL (7 << 0) +#define ST_PG_FDIS1 0x1e20 +#define ST_FDIS_LOCK (1 << 31) + #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 #define SCIS_IRQ11 2 diff --git a/src/soc/intel/alderlake/lockdown.c b/src/soc/intel/alderlake/lockdown.c index e9e4b59..f7b2f3c 100644 --- a/src/soc/intel/alderlake/lockdown.c +++ b/src/soc/intel/alderlake/lockdown.c @@ -48,6 +48,13 @@ write8(pmcbase + GEN_PMCON_B, reg8); } +static void pmc_st_pg_lock(void) +{ + void *pmcbase = pmc_mmio_regs(); + + setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); +} + static void pmc_lockdown_cfg(int chipset_lockdown) { /* PMSYNC */ @@ -57,6 +64,9 @@ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + pmc_st_pg_lock(); } void soc_lockdown_config(int chipset_lockdown) -- To view, visit https://review.coreboot.org/c/coreboot/+/63689 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68343f9af4f34aceae06293c5f87c5eaa3430a60 Gerrit-Change-Number: 63689 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022