coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 18 Apr '22

18 Apr '22

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Change in coreboot[master]: payloads/external/LinuxBoot: Modify Kconfig file and remove older tags
by Elias Souza (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Martin L Roth, Paul Menzel, Christian Walter, Stefan Reinauer. Hello build bot (Jenkins), Martin L Roth, Stefan Reinauer, Christian Walter, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63351 to look at the new patch set (#7). Change subject: payloads/external/LinuxBoot: Modify Kconfig file and remove older tags ...................................................................... payloads/external/LinuxBoot: Modify Kconfig file and remove older tags The u-root repo have modified the name of "master" branch to "main". and remove older tag of u-root and use the new tag. Change-Id: I70c4d064b534b28ea0be987b91a30650debc6ffe Signed-off-by: eliassouza <ratatouillemorde(a)gmail.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.inc 3 files changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63351/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70c4d064b534b28ea0be987b91a30650debc6ffe Gerrit-Change-Number: 63351 Gerrit-PatchSet: 7 Gerrit-Owner: Elias Souza Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... Patch Set 18: (1 comment) Patchset: PS9: > Oh, do we always need a platform driver on the libpayload side anyway? I thought that maybe they could all be handled the same... > If libpayload has individual platform drivers anyway, then yeah, only encode things that we expect may change between SoCs using the same driver (sounds like that's ctrl_base and maybe mmio_size?), and hardcode the rest in the driver (e.g. specific offsets from ctrl_base). For PCIe part, we assume the PCIe buses has be scanned and setup successfully at coreboot stage, so we only need to provide the pci_read/write_config APIs [1] in libpayload for the payloads to access the configuration space of PCIe devices. I think the difference of each non-x86 platform should be how to implement the pci_map_bus() API [2], it will access their hardware and return the base address of specific PCIe device's config space. For MediaTek SoCs, we write the bdf (bus number, device number, function number) information to the register of 'ctrl_base + 0x140' to select the specific device, then the config space of this selected device will be mapped to the address of 'ctrl_base + 0x1000' [3]. Is that ok to pass the ctrl_base and mmio_size to libpayload? But I'm still curious why QC need the mmio_size, since the size of config space for each PCIe device or function should be 4KByte. [1]https://review.coreboot.org/c/coreboot/+/56789/65/payloads/libpayload/dri… [2]https://review.coreboot.org/c/coreboot/+/56789/65/payloads/libpayload/dri… [3]https://review.coreboot.org/c/coreboot/+/56794/67/payloads/libpayload/dri… -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 06:45:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 ) Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63630/comment/955ade97_f96f2423 PS3, Line 103: lpc_set_eiss > > This should do the same as fast_spi_lockdown_cfg(). […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 06:03:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marc Jones <marc(a)marcjonesconsulting.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taniks: Add WiFi SAR table for taniks
by Leo Chou (Code Review) 18 Apr '22

18 Apr '22

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63684 ) Change subject: mb/google/brya/var/taniks: Add WiFi SAR table for taniks ...................................................................... mb/google/brya/var/taniks: Add WiFi SAR table for taniks Add WiFi SAR table for taniks. BUG=b:226690925 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: leo.chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac --- M src/mainboard/google/brya/Kconfig.name M src/mainboard/google/brya/variants/taniks/Makefile.inc A src/mainboard/google/brya/variants/taniks/variant.c 3 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63684/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b79fce6..4ba22c2 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -157,6 +157,7 @@ select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_VELL bool "-> Vell" diff --git a/src/mainboard/google/brya/variants/taniks/Makefile.inc b/src/mainboard/google/brya/variants/taniks/Makefile.inc index 6947beb..3ee0dc9 100644 --- a/src/mainboard/google/brya/variants/taniks/Makefile.inc +++ b/src/mainboard/google/brya/variants/taniks/Makefile.inc @@ -5,3 +5,5 @@ ramstage-y += gpio.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + +ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brya/variants/taniks/variant.c b/src/mainboard/google/brya/variants/taniks/variant.c new file mode 100644 index 0000000..6a79780 --- /dev/null +++ b/src/mainboard/google/brya/variants/taniks/variant.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return "wifi_sar_0.hex"; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/63684 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b52f71b1fe49c02beaa48410495b81661b58fac Gerrit-Change-Number: 63684 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card
by Wisley Chen (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Chen Wisley, Tim Wawrzynczak. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63648 ) Change subject: mb/google/brya/var/anahera{4es}: Enable power saving for Smart Card ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Can you please update the bug with more information about the power saving feature? OK, I updated the bug, and verified the behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/63648 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia17970f717c6ba806d9603031c486bad86e42b37 Gerrit-Change-Number: 63648 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Mon, 18 Apr 2022 03:55:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: crota: enable boot from SSD/ eMMC
by Scott Chao (Code Review) 18 Apr '22

18 Apr '22

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63683 ) Change subject: crota: enable boot from SSD/ eMMC ...................................................................... crota: enable boot from SSD/ eMMC - Fix eMMC reset/ enable GPIO pins. - Fix clk_req and clk_src BUG=b:229437061 BRANCH=none TEST=build and without error Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63683/1 diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 7a6b99e..1360bde 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -84,8 +84,8 @@ end device ref pcie_rp3 on chip soc/intel/common/block/pcie/rtd3 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" register "srcclk_pin" = "1" device generic 0 alias emmc_rtd3 on end end @@ -120,10 +120,10 @@ end end #PCIE8 SD card device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 1 + # Enable CPU PCIE RP 1 using CLK 0 register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_req = 1, - .clk_src = 1, + .clk_req = 0, + .clk_src = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end -- To view, visit https://review.coreboot.org/c/coreboot/+/63683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Gerrit-Change-Number: 63683 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crota: limit dram speed at 4800
by Scott Chao (Code Review) 18 Apr '22

18 Apr '22

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63682 ) Change subject: crota: limit dram speed at 4800 ...................................................................... crota: limit dram speed at 4800 BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63682/1 diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 23d7f3c..7a6b99e 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -19,6 +19,8 @@ chip soc/intel/alderlake + register "max_dram_speed" = "4800" + # Acoustic settings register "acoustic_noise_mitigation" = "1" register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4" -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crota: modify DQ/ DQS table
by Scott Chao (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63681 to look at the new patch set (#4). Change subject: crota: modify DQ/ DQS table ...................................................................... crota: modify DQ/ DQS table BUG=b:229547171 BRANCH=none TEST=pass memory training with error Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: If6acf8cb9474f816374743fd1e800da46958993d --- M src/mainboard/google/brya/variants/crota/memory.c 1 file changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/63681/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6acf8cb9474f816374743fd1e800da46958993d Gerrit-Change-Number: 63681 Gerrit-PatchSet: 4 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask: fix boot beep
by Frank Wu (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Van Chen, John Su, Dtrain Hsu, Ian Feng, Paul Menzel, Tim Wawrzynczak, Amanda Hwang, Felix Held. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63645 ) Change subject: mb/google/brask: fix boot beep ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Gerrit-Change-Number: 63645 Gerrit-PatchSet: 5 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Apr 2022 03:10:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2022