coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/cannonlake: Drop unused LPC BIOS Control macro
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63688 ) Change subject: soc/intel/cannonlake: Drop unused LPC BIOS Control macro ...................................................................... soc/intel/cannonlake: Drop unused LPC BIOS Control macro This patch drops unused LPC BIOS control macros. BUG=b:211954778 TEST=Able to build and boot google/hatch. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6 --- M src/soc/intel/cannonlake/include/soc/lpc.h 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63688/1 diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index a510bc5..c16b732 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -24,10 +24,6 @@ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LGMR 0x98 /* LPC Generic Memory Range */ -#define BIOS_CNTL 0xdc -#define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 1) /* LE */ -#define LPC_BC_EISS (1 << 5) /* EISS */ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/63688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6 Gerrit-Change-Number: 63688 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63687 ) Change subject: soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP) ...................................................................... soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP) This patch implements two APIs to perform LPC/eSPI write protect enable/ disable operation using PCI configuration space register 0xDC (BIOS Controller). BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362 --- M src/soc/intel/common/block/include/intelblocks/lpc_lib.h M src/soc/intel/common/block/lpc/lpc_def.h M src/soc/intel/common/block/lpc/lpc_lib.c 3 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63687/1 diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index 43a3001..32008cc 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -106,4 +106,8 @@ unsigned long current, struct acpi_rsdp *rsdp); const uint8_t *lpc_get_pic_pirq_routing(size_t *num); +/* Enable LPC Write Protect. */ +void lpc_enable_wp(void); +/* Disable LPC Write Protect. */ +void lpc_disable_wp(void); #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */ diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index ab9f2018..47697ca 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -26,6 +26,7 @@ #define LPC_BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ #define LPC_BC_LE (1 << 1) /* LE */ +#define LPC_BC_WPD (1 << 0) /* WPD */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL_CLKRUN_EN (1 << 0) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index a44c2da..1b1e989 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -194,6 +194,31 @@ lpc_set_bios_control_reg(LPC_BC_EISS); } +static void lpc_configure_write_protect(bool status) +{ + const pci_devfn_t dev = PCH_DEV_LPC; + uint8_t bios_cntl; + + bios_cntl = pci_read_config8(dev, LPC_BIOS_CNTL); + if (status) + bios_cntl &= ~LPC_BC_WPD; + else + bios_cntl |= LPC_BC_WPD; + pci_write_config8(dev, LPC_BIOS_CNTL, bios_cntl); +} + +/* Enable LPC Write Protect. */ +void lpc_enable_wp(void) +{ + lpc_configure_write_protect(true); +} + +/* Disable LPC Write Protect. */ +void lpc_disable_wp(void) +{ + lpc_configure_write_protect(false); +} + /* * Set LPC Serial IRQ mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63687 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362 Gerrit-Change-Number: 63687 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63630 to look at the new patch set (#4). Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration This patch implements a helper function to perform LPC registers lock down configuration. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Verified LPC PCI configuration register offset 0xDC bits BILD and LE are set. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/63630/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taniks: Add WiFi SAR table for taniks
by Leo Chou (Code Review) 18 Apr '22

18 Apr '22

Leo Chou has removed Tim Wawrzynczak from this change. ( https://review.coreboot.org/c/coreboot/+/63686 ) Change subject: mb/google/brya/var/taniks: Add WiFi SAR table for taniks ...................................................................... Removed reviewer Tim Wawrzynczak. -- To view, visit https://review.coreboot.org/c/coreboot/+/63686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c50687b53dab78b36ec331bcf07323f1419a8fc Gerrit-Change-Number: 63686 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/brya/var/taniks: Add WiFi SAR table for taniks
by Leo Chou (Code Review) 18 Apr '22

18 Apr '22

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63686 ) Change subject: mb/google/brya/var/taniks: Add WiFi SAR table for taniks ...................................................................... mb/google/brya/var/taniks: Add WiFi SAR table for taniks Add WiFi SAR table for taniks. BUG=b:226690925 TEST=build FW and checked SAR table can load by WiFi driver. Signed-off-by: leo.chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: I7c50687b53dab78b36ec331bcf07323f1419a8fc --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63686/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 4ba22c2..7479eca 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -157,7 +157,7 @@ select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9763E select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX - select CHROMEOS_WIFI_SAR if CHROMEOS + select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_VELL bool "-> Vell" -- To view, visit https://review.coreboot.org/c/coreboot/+/63686 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c50687b53dab78b36ec331bcf07323f1419a8fc Gerrit-Change-Number: 63686 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPI fast speed
by Kenneth Chan (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Rob Barnes, Karthik Ramasubramanian. Kenneth Chan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63685 ) Change subject: mb/google/guybrush/var/dewatt: Override SPI fast speed ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Gerrit-Change-Number: 63685 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 18 Apr 2022 09:02:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Override SPI fast speed
by Kenneth Chan (Code Review) 18 Apr '22

18 Apr '22

Kenneth Chan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63685 ) Change subject: mb/google/guybrush/var/dewatt: Override SPI fast speed ...................................................................... mb/google/guybrush/var/dewatt: Override SPI fast speed After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=b:213403891 TEST=Build and boot to OS in Dewatt board version 2. Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba --- M src/mainboard/google/guybrush/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63685/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index b2cba6e..069da6c 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -140,7 +140,7 @@ config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD hex default 0x4 if BOARD_GOOGLE_GUYBRUSH - default 0x2 if BOARD_GOOGLE_NIPPERKIN + default 0x2 if BOARD_GOOGLE_NIPPERKIN || BOARD_GOOGLE_DEWATT default 0xffffffff help Minimum board version starting which the Override EFS SPI Speed -- To view, visit https://review.coreboot.org/c/coreboot/+/63685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7301d873e36bec4ee46c9d18293f924500ea9aba Gerrit-Change-Number: 63685 Gerrit-PatchSet: 1 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree
by Raihow Shi (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: YH Lin, Subrata Banik, Paul Menzel, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Subrata Banik, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63080 to look at the new patch set (#20). Change subject: mb/google/brask/variants/moli: update overridetree ...................................................................... mb/google/brask/variants/moli: update overridetree Add FW_CONFIG STORAGE and probe for UNKNOWN, NVME and eMMC. BUG=b:220039297 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 23 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/63080/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 20 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brask/variants/moli: update overridetree
by Raihow Shi (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: YH Lin, Subrata Banik, Paul Menzel, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Subrata Banik, Tim Wawrzynczak, Eric Lai, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63080 to look at the new patch set (#19). Change subject: mb/google/brask/variants/moli: update overridetree ...................................................................... mb/google/brask/variants/moli: update overridetree Add FW_CONFIG STORAGE and probe for NVME and eMMC. BUG=b:220039297 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 23 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/63080/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/63080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If83031edcd90ea746704590765102b9b0dee03c1 Gerrit-Change-Number: 63080 Gerrit-PatchSet: 19 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Subrata Banik (Code Review) 18 Apr '22

18 Apr '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sridhar Siricilla, Nick Vaccaro, Eric Lai, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63552/comment/ff114c96_3dfe0e34 PS4, Line 9: calls into > Just “calls”? Ack https://review.coreboot.org/c/coreboot/+/63552/comment/0e9e9c09_db3cc418 PS4, Line 12: Without this patch the PMC IPC timeout issue is seen > Currently, the PMC IPC times out while sending the USB-C (0xA7) command during … Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 18 Apr 2022 08:41:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2022