coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/osiris: Generate SPD ID for supported parts
by Eric Lai (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: David Wu, Ren Kuo, Tim Wawrzynczak, Nick Vaccaro. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63706 ) Change subject: mb/google/brya/var/osiris: Generate SPD ID for supported parts ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Gerrit-Change-Number: 63706 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:44:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63627 ) Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63627/comment/019db62d_b9352f2d PS9, Line 63: printk(BIOS_ERR, "SPI Cycle pending for too long!\n"); > Since the die() is removed, do we still need this debug msg? > As the similar debug msg has been printed in the function fast_spi_cycle_in_progress(): > https://review.coreboot.org/c/coreboot/+/63624/6/src/soc/intel/common/block… I agree -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:43:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/craask: Add Memory for proto stage
by Tyler Wang (Code Review) 19 Apr '22

19 Apr '22

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63712 ) Change subject: mb/google/brya/var/craask: Add Memory for proto stage ...................................................................... mb/google/brya/var/craask: Add Memory for proto stage Craask will use Micron MT62F512M32D2DR-031 WT:B. Add it to the parts list and regenerate the memory IDs using part_id_gen. BUG=None TEST=None Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a --- M src/mainboard/google/brya/variants/craask/memory/Makefile.inc M src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt 3 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/63712/1 diff --git a/src/mainboard/google/brya/variants/craask/memory/Makefile.inc b/src/mainboard/google/brya/variants/craask/memory/Makefile.inc index eace2e4..247a1bc 100644 --- a/src/mainboard/google/brya/variants/craask/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/craask/memory/Makefile.inc @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/craask/memory src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt index fa24790..e3b10a0 100644 --- a/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt @@ -1 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/craask/memory src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt + DRAM Part Name ID to assign +MT62F512M32D2DR-031 WT:B 0 (0000) diff --git a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt index 9621137..d1e64f1 100644 --- a/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt @@ -9,3 +9,4 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +MT62F512M32D2DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/63712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a Gerrit-Change-Number: 63712 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Lean Sheng Tan, Eric Lai, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63627 to look at the new patch set (#10). Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration This patch performs additional SPI lock configuration as per Intel Flash Security Specification. BUG=b:211954778 TEST=Able to build google/brya and verified all flash security recommendations are being met. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 --- M src/soc/intel/common/pch/lockdown/lockdown.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/63627/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/coreboot_table.c: Make sure entries are aligned
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63710 ) Change subject: lib/coreboot_table.c: Make sure entries are aligned ...................................................................... Patch Set 2: -Code-Review (1 comment) Patchset: PS2: > This won't work for memranges for instance... It will, but it's still akward... -- To view, visit https://review.coreboot.org/c/coreboot/+/63710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Gerrit-Change-Number: 63710 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:32:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add WIFI SAR support for tarlo
by Joey Peng (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak. Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63644 to look at the new patch set (#5). Change subject: mb/google/brya/var/taeko: Add WIFI SAR support for tarlo ...................................................................... mb/google/brya/var/taeko: Add WIFI SAR support for tarlo Taeko/Tarlo uses the WIFI_SAR_ID field in FW_CONFIG to pick which SAR table to load. BUG=b:226684990 TEST=emerge-brya coreboot Cq-Depend: chrome-internal:4676926, chrome-intaenal:4686953 Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: I9852553f5c91494db845d45a94e2566248538bba --- M src/mainboard/google/brya/variants/taeko/variant.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/63644/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/63644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9852553f5c91494db845d45a94e2566248538bba Gerrit-Change-Number: 63644 Gerrit-PatchSet: 5 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/taeko: Add WIFI SAR support for tarlo
by Joey Peng (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: YH Lin, Tim Wawrzynczak. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63644 ) Change subject: mb/google/brya/var/taeko: Add WIFI SAR support for tarlo ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/63644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9852553f5c91494db845d45a94e2566248538bba Gerrit-Change-Number: 63644 Gerrit-PatchSet: 4 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:29:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/coreboot_table.c: Make sure entries are aligned
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63710 ) Change subject: lib/coreboot_table.c: Make sure entries are aligned ...................................................................... Patch Set 2: Code-Review-2 (1 comment) Patchset: PS2: This won't work for memranges for instance... -- To view, visit https://review.coreboot.org/c/coreboot/+/63710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Gerrit-Change-Number: 63710 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:19:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Lean Sheng Tan (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, Kangheui Won, harsha.b.r(a)intel.com, Paul Menzel, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Ronak Kanabar, Usha P. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62323 ) Change subject: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Isnt it better to fix this in FSP instead? -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:14:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/coreboot_table.c: Use align macro
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63711 ) Change subject: lib/coreboot_table.c: Use align macro ...................................................................... lib/coreboot_table.c: Use align macro Change-Id: Ie874fe2c023157fad0adc021faa45e70822208da Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/coreboot_table.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/63711/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 402b41b..217f370 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -37,9 +37,7 @@ { struct lb_header *header; - /* 16 byte align the address */ - addr += 15; - addr &= ~15; + addr = ALIGN_UP(addr, 16); header = (void *)addr; header->signature[0] = 'L'; -- To view, visit https://review.coreboot.org/c/coreboot/+/63711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie874fe2c023157fad0adc021faa45e70822208da Gerrit-Change-Number: 63711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit April 2022