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Change subject: [NEEDTEST]soc/amd/non-car: Don't add bootblock cbfs file
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Patch Set 11: Code-Review+1
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Change subject: lib: Check for non-existent DIMMs in check_if_dimm_changed
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Patch Set 10: Code-Review+2
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Change subject: Kconfig: Add an option to skip adding a cbfs bootblock on x86
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Patch Set 4: Code-Review+1
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Change subject: mb/google/brya: Reset XHCI controller while preparing for S5
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Patch Set 5:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63552/comment/e70e6645_96d9b62d
PS4, Line 12: the PMC IPC timeout issue
> > As you use “the”, is it a common known problem? Is there some errata? […]
Ah, I didn’t check, but also I shouldn’t have to. Can you add that information to the commit message please?
https://review.coreboot.org/c/coreboot/+/63552/comment/805d9c52_f5425d0f
PS4, Line 34: active USB port
> > Excuse my ignorance, does “active” mean, something needs to be connected to the port? […]
Done
https://review.coreboot.org/c/coreboot/+/63552/comment/b396f049_b66f3248
PS4, Line 37: SMI handler
> > Why does this have to be done in SMM? […]
Sorry, thinking error on my part. coreboot of course does not run anymore during shutdown (besides the installed handlers).
But, why can’t this be worked around/fixed in the OS driver? I thought, we try to avoid SMM?
https://review.coreboot.org/c/coreboot/+/63552/comment/550a2d7a_13077f59
PS4, Line 9: This patch calls into `xhci_host_reset()` function to perform XHCI
: controller reset.
:
: Without this patch the PMC IPC timeout issue is seen while sending the
: USB-C (0xA7) command during poweron from S5 (S5->S4->S3->S0).
:
: On Brya variants, poweron from S5 state results in PMC error while
: sending PMC IPC (0xA7) to USB-C active ports, log here:
:
: localhost ~ # cbmem -c | grep ERROR
:
: [ERROR] PMC IPC timeout after 1000 ms
: [ERROR] PMC IPC command 0x200a7 failed
: [ERROR] pmc_send_ipc_cmd failed
: [ERROR] Failed to setup port:0 to initial state
: [ERROR] PMC IPC timeout after 1000 ms
: [ERROR] PMC IPC command 0x200a7 failed
: [ERROR] pmc_send_ipc_cmd failed
: [ERROR] Failed to setup port:1 to initial state
: [ERROR] PMC IPC timeout after 1000 ms
: [ERROR] PMC IPC command 0x20a0 failed
:
: This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).
:
: During poweron the state of USB ports are not the same between S5 and G3
: and it appears that the active USB port still is in U3 (suspend) while
: PMC tries to send the IPC command, which results in a timeout.
:
: This patch utilises the S5 SMI handler to reset the XHCI controller
: using `xhci_host_reset()` prior entering into the S5, it helps to
: restore the port state to active hence, no PMC timeout is seen with
: this code change.
Yes, sorry for being ambiguous. I’d have removed
> This patch calls `xhci_host_reset()` function to perform XHCI controller reset.
in the beginning. But the current commit message reads fine.
https://review.coreboot.org/c/coreboot/+/63552/comment/6f27912f_288b8d1b
PS4, Line 41:
> > Does resetting add anything to the shutdown time? (Boottime should be unaffected?) […]
Ack
File src/mainboard/google/brya/smihandler.c:
https://review.coreboot.org/c/coreboot/+/63552/comment/ab2e3927_4dc2f7b2
PS4, Line 15: /* USB sleep preparations */
Something like:
> Work around bug in PMC controller with S5
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Change subject: Makefile.inc: Add x86 bootblock as a separate target
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Patch Set 14: Code-Review+1
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Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
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Patch Set 9: Code-Review+2
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Change subject: soc/intel/common/block/cse: Simplify CSE final ops
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