coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Ronak Kanabar (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, Kangheui Won, harsha.b.r(a)intel.com, Paul Menzel, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Lean Sheng Tan, Usha P. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62323 ) Change subject: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... Patch Set 7: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62323/comment/ba2ff3ae_eaa39b3e PS6, Line 7: soc/intel/common : > Please remove the space. Done https://review.coreboot.org/c/coreboot/+/62323/comment/0085bc79_48ae4d17 PS6, Line 11: CPUID_EXTENDED_CPU_TOPOLOGY(0x0B) > Please add a space before (. (Also in the rest of the text. […] Done https://review.coreboot.org/c/coreboot/+/62323/comment/e4d89785_2a73cb0d PS6, Line 17: provide > provides Done https://review.coreboot.org/c/coreboot/+/62323/comment/187d15f2_1fd19e74 PS6, Line 19: inorder > in order Done https://review.coreboot.org/c/coreboot/+/62323/comment/e234e590_ad76af4a PS6, Line 19: Coreboot > coreboot Done https://review.coreboot.org/c/coreboot/+/62323/comment/6e7444f6_80766779 PS6, Line 25: Coreboot > coreboot Done https://review.coreboot.org/c/coreboot/+/62323/comment/e7c97a22_5fe64a92 PS6, Line 29: Solve > solve Done https://review.coreboot.org/c/coreboot/+/62323/comment/bd5dac23_fbbff5f6 PS6, Line 42: didn't observe hang while booting > observe system boots (no hang) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:04:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Ronak Kanabar (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, Kangheui Won, harsha.b.r(a)intel.com, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Lean Sheng Tan, Ronak Kanabar, Usha P. Hello V Sowmya, build bot (Jenkins), Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Angel Pons, Krishna P Bhat D, Lean Sheng Tan, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62323 to look at the new patch set (#7). Change subject: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY (0x0B) returns data related to number of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2 (0x1F) provides more granular information regarding Die, package etc. coreboot uses V2 to in order to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and observe system boots (no hang). Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62323/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: coreboot_tables: Add PCIe info to coreboot table
by Jianjun Wang (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Nico Huber, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 ) Change subject: coreboot_tables: Add PCIe info to coreboot table ...................................................................... Patch Set 19: (1 comment) Patchset: PS9: > coreboot table entry formats should generally not be changed after they have been introduced (althou […] According to the PCI spec, a PCI bus may have up to 32 devices, and each device may have 8 functions in maxmium, the total size of configuration space for each bus will be 32 * 8 * 4K = 1024K, so I guess the reason why Qualcomm set the mmio_size to 1MB is to mapping the whole bus (but MediaTek only mapping the minimum space each time). Anyway, I think this should be a constant value, I don't know why Qualcomm need to pass it to libpayload. @Shelley, do you have any suggestions? Could you help to clarify these questions? Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/63251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Gerrit-Change-Number: 63251 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 10:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib/coreboot_table.c: Make sure entries are aligned
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/63710 ) Change subject: lib/coreboot_table.c: Make sure entries are aligned ...................................................................... lib/coreboot_table.c: Make sure entries are aligned Unaligned pointer access may be invalid code on some architectures. By padding each entry size to 64bit it is possible to ensure each table entry is aligned to the size of pointers of the payload. This for instance the case when coreboot runs as 32bit code but the payload is 64bit. Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/coreboot_table.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63710/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Gerrit-Change-Number: 63710 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/coreboot_table.c: Make sure entries are aligned
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63710 ) Change subject: lib/coreboot_table.c: Make sure entries are aligned ...................................................................... lib/coreboot_table.c: Make sure entries are aligned Unaligned pointer access may be invalid code on some architectures. By padding each entry size to 64bit it is possible to ensure each table entry is aligned to the size of pointers of the payload. This for instance the case when coreboot runs as 32bit code but the payload is 64bit. Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/coreboot_table.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63710/1 diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3ceab37..fdea98d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -73,6 +73,12 @@ { struct lb_record *rec; rec = lb_last_record(header); + /* + * Pad all record sizes to make sure each record is aligned to the size of pointers. + * Because the environment decoding the coreboot tables can have a different pointer + * size than coreboot, simply use 64bit all the time. + */ + rec->size = ALIGN_UP(rec->size, 8); if (header->table_entries) header->table_bytes += rec->size; rec = lb_last_record(header); -- To view, visit https://review.coreboot.org/c/coreboot/+/63710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Gerrit-Change-Number: 63710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: sec/intel/txt: Use variable
by Paul Menzel (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Arthur Heymans. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63062 ) Change subject: sec/intel/txt: Use variable ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63062/comment/ef269e3e_237b0c63 PS2, Line 7: sec/intel/txt: Use variable Maybe: > Use variable `bios_acm_error` -- To view, visit https://review.coreboot.org/c/coreboot/+/63062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ee61fb9533b90ddb1a1592d5d9945761739ddb6 Gerrit-Change-Number: 63062 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:58:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Angel Pons (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, Kangheui Won, harsha.b.r(a)intel.com, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Lean Sheng Tan, Ronak Kanabar, Usha P. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62323 ) Change subject: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:58:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Paul Menzel (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, Usha P. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62323 ) Change subject: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... Patch Set 6: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62323/comment/fdbac5b8_5e77bc60 PS6, Line 7: soc/intel/common : Please remove the space. https://review.coreboot.org/c/coreboot/+/62323/comment/e261ef6d_a8edd80d PS6, Line 11: CPUID_EXTENDED_CPU_TOPOLOGY(0x0B) Please add a space before (. (Also in the rest of the text.) https://review.coreboot.org/c/coreboot/+/62323/comment/825c1ec2_2c7f8099 PS6, Line 17: provide provides https://review.coreboot.org/c/coreboot/+/62323/comment/456e0067_29be2b61 PS6, Line 19: inorder in order https://review.coreboot.org/c/coreboot/+/62323/comment/5654a165_3f17985d PS6, Line 19: Coreboot coreboot https://review.coreboot.org/c/coreboot/+/62323/comment/4de1d73a_dc5f5083 PS6, Line 25: Coreboot coreboot https://review.coreboot.org/c/coreboot/+/62323/comment/212b578f_daef9c8b PS6, Line 29: Solve solve https://review.coreboot.org/c/coreboot/+/62323/comment/2f549299_a6e00c4b PS6, Line 42: didn't observe hang while booting observe system boots (no hang) -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:57:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Lean Sheng Tan (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63627 ) Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... Patch Set 9: Code-Review+1 (1 comment) File src/soc/intel/common/pch/lockdown/lockdown.c: https://review.coreboot.org/c/coreboot/+/63627/comment/25cc4216_e0b95c67 PS9, Line 63: printk(BIOS_ERR, "SPI Cycle pending for too long!\n"); Since the die() is removed, do we still need this debug msg? As the similar debug msg has been printed in the function fast_spi_cycle_in_progress(): https://review.coreboot.org/c/coreboot/+/63624/6/src/soc/intel/common/block… -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:54:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
by Paul Menzel (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63709 ) Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/brya0/gpio.c: https://review.coreboot.org/c/coreboot/+/63709/comment/e54b39bb_82fd1ca9 PS1, Line 132: /* : * D1 : ISH_GP1 ==> FP_RST_ODL : * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. : * To ensure proper power sequencing for the FPMCU device, reset signal is driven low : * early on in bootblock, followed by enabling of power. Reset signal is deasserted : * later on in ramstage. Since reset signal is asserted in bootblock, it results in : * FPMCU not working after a S3 resume. This is a known issue. : */ Please wrap the lines earlier, and also follow the [commenting style](https://doc.coreboot.org/contributing/coding_style.html#commenting). -- To view, visit https://review.coreboot.org/c/coreboot/+/63709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Gerrit-Change-Number: 63709 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:52:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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