coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans, Eric Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Angel Pons, Arthur Heymans, Nick Vaccaro, Lean Sheng Tan, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63518 to look at the new patch set (#7). Change subject: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent ...................................................................... soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. End Of Firmware. The system agent `.final` operation ensures locking the PAM register hence, skip dedicated calling into `sa_lock_pam()` from the SoC `finalize.c` file when coreboot decides to skip FspNotifyApi() calls. BUG=b:211954778 TEST=Able to build google/brya with these changes and coreboot log with this code change as below with ADL SoC skip calling into FspNotifyAPIs: [INFO ] Finalize devices... [DEBUG] PCI: 00:00.0 final > localhost ~ # lspci -xxx | less 00:00.0 Host bridge: Device 8086:4601 (rev 04) Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set (meaning locked). Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/common/block/systemagent/systemagent.c 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63518/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/smbus: Add `finalize` operation for smbus
by Felix Singer (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63640 ) Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/smbus/smbus.c: https://review.coreboot.org/c/coreboot/+/63640/comment/312c1c33_585f9e6c PS4, Line 88: smbus_final Suggestion: finalize_smbus -- To view, visit https://review.coreboot.org/c/coreboot/+/63640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie945680049514e6c5d797790a381a6946e836926 Gerrit-Change-Number: 63640 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 12:03:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sridhar Siricilla, Nick Vaccaro, Eric Lai, Felix Held. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63552 to look at the new patch set (#6). Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... mb/google/brya: Reset XHCI controller while preparing for S5 This patch calls `xhci_host_reset()` function to perform XHCI controller reset. Currently, the PMC IPC times out while sending the USB-C (0xA7) command during poweron from S5 (S5->S4->S3->S0). On Brya variants, poweron from S5 state results in PMC error while sending PMC IPC (0xA7) to USB-C active ports, log here: localhost ~ # cbmem -c | grep ERROR [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:0 to initial state [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:1 to initial state [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x20a0 failed This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0). During poweron the state of USB ports are not the same between S5 and G3 and it appears that the active USB port still is in U3 (suspend) while PMC tries to send the IPC command, which results in a timeout. This patch utilises the S5 SMI handler to reset the XHCI controller using `xhci_host_reset()` prior entering into the S5, it helps to restore the port state to active hence, no PMC timeout is seen with this code change. Supporting Doc=Intel expected to release a TA (Technical Advisory) document to acknowledge this observation and supported W/A for ADL generation platforms. Till that time, keeping this W/A as part of the google/brya specific mainboard alone. Note: other ADL-SoC based mainboards might need to apply the similar W/A. BUG=b:227289581 TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7) during resume from S5. Total Time: 1,045,855 localhost ~ # cbmem -c | grep ERROR No PMC timeout error is observed with this CL. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 --- M src/mainboard/google/brya/smihandler.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63552/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/brya: Reset XHCI controller while preparing for S5
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Sridhar Siricilla, Nick Vaccaro, Eric Lai, Felix Held. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63552 ) Change subject: mb/google/brya: Reset XHCI controller while preparing for S5 ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63552/comment/a3866457_f26347be PS4, Line 12: the PMC IPC timeout issue > Ah, I didn’t check, but also I shouldn’t have to. […] Ack https://review.coreboot.org/c/coreboot/+/63552/comment/4223cfa0_bebaf122 PS4, Line 37: SMI handler > Sorry, thinking error on my part. coreboot of course does not run anymore during shutdown (besides the installed handlers). > > But, why can’t this be worked around/fixed in the OS driver? fixing in FW is comparatively easier 😊 and could apply MB specific W/As as well. > I thought, we try to avoid SMM? Anyway we have this SMI handler where the control is expected to reach with `shutdown` hence, we are just adding one operation to reset the XHCI controller using the same handler. Avoiding SMM is a wish for sure, but currently we are using it as is, is my point. I hope you are good with it for now? File src/mainboard/google/brya/smihandler.c: https://review.coreboot.org/c/coreboot/+/63552/comment/31cd21df_f4e8cfc3 PS4, Line 15: /* USB sleep preparations */ > Something like: > > > Work around bug in PMC controller with S5 this is not PMC controller problem, rather XHCI controller is unable to reflect its state proper upon poweron from S5, hence, added the correct statement -- To view, visit https://review.coreboot.org/c/coreboot/+/63552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf06a64f055a0cee3659b410652082f31e18e149 Gerrit-Change-Number: 63552 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:55:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/cannonlake: Drop unused LPC BIOS Control macro
by Lean Sheng Tan (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans, Eric Lai, Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63688 ) Change subject: soc/intel/cannonlake: Drop unused LPC BIOS Control macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63688 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6 Gerrit-Change-Number: 63688 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:53:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Implement PCH lock down configuration
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63692 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Implement PCH lock down configuration ...................................................................... soc/intel/alderlake: Implement PCH lock down configuration This patch implements a function to enable IOSF Primary Trunk Clock Gating. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c --- M src/soc/intel/alderlake/lockdown.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/63692/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c Gerrit-Change-Number: 63692 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63691 to look at the new patch set (#3). Change subject: soc/intel/alderlake: Implement PMC feature lock ...................................................................... soc/intel/alderlake: Implement PMC feature lock This patch locks PMC features like: debug mode configuration and host read access to PMC XRAM. BUG=b:211954778 TEST=Able to build and boot google/redrix to OS. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c --- M src/soc/intel/alderlake/include/soc/pmc.h M src/soc/intel/alderlake/lockdown.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/63691/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Gerrit-Change-Number: 63691 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Marc Jones, Tim Wawrzynczak, Angel Pons, Arthur Heymans, Eric Lai, Lean Sheng Tan. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63630 ) Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63630/comment/c6935977_d9092c9a PS4, Line 14: configuration register offset 0xDC bits BILD and LE are set. > Could you please test what happens after setting the WPD bit from the OS? For example, using setpci: > > sudo setpci -s 0:1f.0 0xdc.b=0x0a > > I ask because I had troubles with the SPI PCI device where the SMI handler would fail to clear the SMI source, and the system would hang (it would be stuck in a SMI storm). See CB:50754 for the fix. I don't think this issue can happen with LPC, but I'd appreciate if you could test just to make sure. I don't see any problem while running `setpci` from OS as requested. -- To view, visit https://review.coreboot.org/c/coreboot/+/63630 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8 Gerrit-Change-Number: 63630 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: commonlib/coreboot_tables.h: Don't pack structs
by Nico Huber (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Patrick Rudolph, Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63714 ) Change subject: commonlib/coreboot_tables.h: Don't pack structs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb756ab4e3562512e1160224678a6de23f3b84ec Gerrit-Change-Number: 63714 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:31:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: commonlib/coreboot_tables.h: Don't pack structs
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63714 ) Change subject: commonlib/coreboot_tables.h: Don't pack structs ...................................................................... commonlib/coreboot_tables.h: Don't pack structs Packing structs will result in unaligned sizes, possible causing problems for other entries. Change-Id: Ifb756ab4e3562512e1160224678a6de23f3b84ec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/coreboot_tables.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/63714/1 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 206ddb4..7666588 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -552,7 +552,7 @@ uint32_t ppi_address; /* Address of ACPI PPI communication buffer */ uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ uint8_t ppi_version; /* BCD encoded */ -} __packed; +}; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/63714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb756ab4e3562512e1160224678a6de23f3b84ec Gerrit-Change-Number: 63714 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022