coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

1 participants
5879 discussions

Change in coreboot[master]: mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63638 ) Change subject: mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750 ...................................................................... mb/google/brya/var/anahera{4es}: select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9750 to disable ASPM L0s. BUG=b:229213455 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/63638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index b79fce6..3028aa1 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -13,6 +13,7 @@ bool "-> Anahera" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GFX_GENERIC select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE @@ -21,6 +22,7 @@ bool "-> Anahera4ES" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GFX_GENERIC select HAVE_PCIE_WWAN select HAVE_WWAN_POWER_SEQUENCE -- To view, visit https://review.coreboot.org/c/coreboot/+/63638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie89fa6c66974284063cd25ae8097db94a93326ca Gerrit-Change-Number: 63638 Gerrit-PatchSet: 2 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Kconfig: Make HAVE_EM100_SUPPORT invisible
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63676 ) Change subject: Kconfig: Make HAVE_EM100_SUPPORT invisible ...................................................................... Kconfig: Make HAVE_EM100_SUPPORT invisible This is a property of a platform and should not be exposed to the user. Change-Id: I34f9097d40b2bf732cecf30bf13ba5a413dd53a5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63676 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index d57ce90..dc81979 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1210,7 +1210,7 @@ `pragma Debug`. config HAVE_EM100_SUPPORT - bool "Platform can support the Dediprog EM100 SPI emulator" + bool help This is enabled by platforms which can support using the EM100. -- To view, visit https://review.coreboot.org/c/coreboot/+/63676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34f9097d40b2bf732cecf30bf13ba5a413dd53a5 Gerrit-Change-Number: 63676 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: Kconfig: Make HAVE_EM100_SUPPORT invisible
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63676 ) Change subject: Kconfig: Make HAVE_EM100_SUPPORT invisible ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34f9097d40b2bf732cecf30bf13ba5a413dd53a5 Gerrit-Change-Number: 63676 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 13:04:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/x86/Kconfig*: Guard with ARCH_X86
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63673 ) Change subject: cpu/x86/Kconfig*: Guard with ARCH_X86 ...................................................................... cpu/x86/Kconfig*: Guard with ARCH_X86 None of these options make sense on different ARCH. Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63673 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/Kconfig M src/cpu/x86/Kconfig.debug_cpu 2 files changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index d5c688d..658d2aa 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -1,3 +1,5 @@ +if ARCH_X86 + config PARALLEL_MP def_bool y depends on !LEGACY_SMP_INIT @@ -194,3 +196,5 @@ Enables the new method of locating struct cpu_info. This new method uses the %gs segment to locate the cpu_info pointer. The old method relied on the stack being CONFIG_STACK_SIZE aligned. + +endif # ARCH_X86 diff --git a/src/cpu/x86/Kconfig.debug_cpu b/src/cpu/x86/Kconfig.debug_cpu index f8ed370..7edb60f 100644 --- a/src/cpu/x86/Kconfig.debug_cpu +++ b/src/cpu/x86/Kconfig.debug_cpu @@ -1,3 +1,5 @@ +if ARCH_X86 + config HAVE_DEBUG_CAR bool @@ -11,3 +13,5 @@ config DEBUG_SMM_RELOCATION bool "Debug SMM relocation code" depends on HAVE_SMI_HANDLER && SMM_ASEG + +endif # ARCH_X86 -- To view, visit https://review.coreboot.org/c/coreboot/+/63673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie90ad24ff9013e38c42f10285cc3b546a3cc0571 Gerrit-Change-Number: 63673 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: payloads/depthcharge: enable LP_CHROMEOS in depthcharge
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63240 ) Change subject: payloads/depthcharge: enable LP_CHROMEOS in depthcharge ...................................................................... payloads/depthcharge: enable LP_CHROMEOS in depthcharge Fix standslone build failure after depthcharge patch https://crrev.com/c/3461454 merge. BUG=chrome-os-partner:226438207 TEST=Compiled brya and redrix in standalone mode. Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63240 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> --- M payloads/external/depthcharge/Makefile 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Jakub Czapiga: Looks good to me, approved diff --git a/payloads/external/depthcharge/Makefile b/payloads/external/depthcharge/Makefile index 23595e5..687e9f0 100644 --- a/payloads/external/depthcharge/Makefile +++ b/payloads/external/depthcharge/Makefile @@ -68,6 +68,8 @@ false) echo $(DEPTHCHARGE_LIBPAYLOAD_MSG) cp $(libpayload_config) $(libpayload_dir)/.config + (grep -q '^\s*CONFIG_LP_CHROMEOS=' $(libpayload_dir)/.config) || \ + (echo "CONFIG_LP_CHROMEOS=y" >> $(libpayload_dir)/.config) $(MAKE) -C $(libpayload_dir) olddefconfig $(MAKE) -C $(libpayload_dir) $(MAKE) -C $(libpayload_dir) install DESTDIR=$(libpayload_install_dir) -- To view, visit https://review.coreboot.org/c/coreboot/+/63240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bb2ce42a314e05ef22ea7b8abc067d6361d511 Gerrit-Change-Number: 63240 Gerrit-PatchSet: 8 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/alderlake: Enable Pre Reset CPU Telemetry
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63616 ) Change subject: soc/intel/alderlake: Enable Pre Reset CPU Telemetry ...................................................................... soc/intel/alderlake: Enable Pre Reset CPU Telemetry Insert CSE timestamps to coreboot timestamp table. BUG=b:182575295 TEST=Boot to OS on Brya Redrix board. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63616 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 35fd2f7..dbcb509 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -111,6 +111,7 @@ select SOC_INTEL_COMMON_RESET select SOC_INTEL_CSE_SEND_EOP_EARLY select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY if SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63616 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbea7155a294e0039a5bd1d16588775e90a29ae3 Gerrit-Change-Number: 63616 Gerrit-PatchSet: 4 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/nissa: Add gpio lock pins
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63568 ) Change subject: mb/google/nissa: Add gpio lock pins ...................................................................... mb/google/nissa: Add gpio lock pins Followed the Brya series to lock the gpio pins in baseboard. Variant should honor locked gpios from baseboard, but not the last. Variant can add more gpios to lock if needed. BUG=b:216671701 TEST='emerge-nissa coreboot chromeos-bootimage', flash and verify that nivviks boots successfully to kernel. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63568 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/nissa/gpio.c 1 file changed, 48 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c index 06fc1b7..ba3c8c5 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gpio.c @@ -29,13 +29,13 @@ /* A12 : NC */ PAD_NC(GPP_A12, NONE), /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* A14 : USB_OC1# ==> NC */ PAD_NC(GPP_A14, NONE), /* A15 : USB_OC2# ==> NC */ PAD_NC(GPP_A15, NONE), /* A16 : USB_OC3# ==> NC */ - PAD_NC(GPP_A16, NONE), + PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), /* A17 : NC */ PAD_NC(GPP_A17, NONE), /* A18 : NC */ @@ -58,17 +58,17 @@ /* B2 : NC */ PAD_NC(GPP_B2, NONE), /* B3 : NC */ - PAD_NC(GPP_B3, NONE), + PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG), /* B4 : NC */ - PAD_NC(GPP_B4, NONE), + PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG), /* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B7 : I2C3_SDA ==> SOC_I2C_AUDIO_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : I2C3_SCL ==> SOC_I2C_AUDIO_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B9 : Not available */ PAD_NC(GPP_B9, NONE), /* B10 : Not available */ @@ -80,13 +80,13 @@ /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> GPP_B14_STRAP */ - PAD_NC(GPP_B14, NONE), + PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), /* B15 : NC */ - PAD_NC(GPP_B15, NONE), + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> SOC_I2C_TCHPAD_SDA */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), /* B17 : I2C5_SCL ==> SOC_I2C_TCHPAD_SCL */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), /* B18 : GPP_B18 ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), /* B19 : Not available */ @@ -118,13 +118,13 @@ PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), /* D0 : NC */ - PAD_NC(GPP_D0, NONE), + PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG), /* D1 : NC */ - PAD_NC(GPP_D1, NONE), + PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG), /* D2 : NC */ - PAD_NC(GPP_D2, NONE), + PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG), /* D3 : ISH_GP3 ==> WCAM_RST_L */ - PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_D4, 1, DEEP), /* D5 : NC */ @@ -136,34 +136,34 @@ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : NC */ - PAD_NC(GPP_D9, NONE), + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ - PAD_NC(GPP_D10, NONE), + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), /* D11 : NC */ - PAD_NC(GPP_D11, NONE), + PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ - PAD_NC(GPP_D12, NONE), + PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), /* D13 : NC */ - PAD_NC(GPP_D13, NONE), + PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG), /* D14 : NC */ - PAD_NC(GPP_D14, NONE), + PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */ - PAD_CFG_GPO(GPP_D15, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */ - PAD_CFG_GPO(GPP_D16, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG), /* D17 : NC */ - PAD_NC(GPP_D17, NONE), + PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : NC */ - PAD_NC(GPP_D18, NONE), + PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* E0 : NC */ PAD_NC(GPP_E0, NONE), /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> MEM_STRAP_2 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* E4 : NC */ @@ -171,21 +171,21 @@ /* E5 : NC */ PAD_NC(GPP_E5, NONE), /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ - PAD_NC(GPP_E6, NONE), + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), /* E7 : NC */ PAD_NC(GPP_E7, NONE), /* E8 : GPP_E8 ==> WLAN_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* E9 : NC */ - PAD_NC(GPP_E9, NONE), + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), /* E10 : NC */ - PAD_NC(GPP_E10, NONE), + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : NC */ - PAD_NC(GPP_E11, NONE), + PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG), /* E13 : NC */ - PAD_NC(GPP_E13, NONE), + PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : NC */ @@ -193,7 +193,7 @@ /* E16 : NC */ PAD_NC(GPP_E16, NONE), /* E17 : NC */ - PAD_NC(GPP_E17, NONE), + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : NC */ PAD_NC(GPP_E18, NONE), /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ @@ -230,21 +230,21 @@ /* F10 : GPP_F10 ==> GPP_F10_STRAP */ PAD_NC(GPP_F10, NONE), /* F11 : NC */ - PAD_NC(GPP_F11, NONE), + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), /* F12 : GSXDOUT ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_F12, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_F13, NONE, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ - PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG), /* F16 : NC */ - PAD_NC(GPP_F16, NONE), + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ - PAD_CFG_GPI_SCI(GPP_F17, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_SCI_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : Not available */ PAD_NC(GPP_F19, NONE), /* F20 : Not available */ @@ -263,11 +263,11 @@ /* H2 : GPP_H2_STRAP */ PAD_NC(GPP_H2, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI_SCI_LOW(GPP_H3, NONE, DEEP, EDGE_SINGLE), + PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG), /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG), /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG), /* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */ @@ -281,9 +281,9 @@ /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H12 : UART0_RTS# ==> SD_PERST_L */ - PAD_CFG_GPO(GPP_H12, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H12, 1, LOCK_CONFIG), /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ - PAD_CFG_GPO(GPP_H13, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG), /* H14 : Not available */ PAD_NC(GPP_H14, NONE), /* H15 : NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63568 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib34ca287596a6958407a944d0caf53f4bcc60d9b Gerrit-Change-Number: 63568 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration
by Lean Sheng Tan (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63627 ) Change subject: soc/intel/cmn/pch/lockdown: Perform additional SPI lock configuration ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63627 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I922db8b46ac0d0523b91fc5aced88e38c8d8a560 Gerrit-Change-Number: 63627 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 13:02:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya: Add Kconfig for TPM I2C bus
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63635 ) Change subject: mb/google/brya: Add Kconfig for TPM I2C bus ...................................................................... mb/google/brya: Add Kconfig for TPM I2C bus Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:229200525 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63635 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 0c76482..331041f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -120,6 +120,7 @@ default 0x1 if BOARD_GOOGLE_KINOX default 0x0 if BOARD_GOOGLE_CRAASK default 0x1 if BOARD_GOOGLE_CROTA + default 0x1 if BOARD_GOOGLE_MOLI config DRIVER_TPM_I2C_ADDR hex 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8054e623fb0c3c549c3373982ce9d4fbd57e0fd7 Gerrit-Change-Number: 63635 Gerrit-PatchSet: 5 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driver
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63617 ) Change subject: mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driver ...................................................................... mb/google/brya/var/crota: Kconfig: Select TPM I2C bus driver Add TPM I2C for crota to avoid TPM I2C fail. BUG=b:226315394 TEST=USE="project_crota emerge-brya coreboot" and verify it builds without error. Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63617 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 0fafc2f..0c76482 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -119,6 +119,7 @@ default 0x1 if BOARD_GOOGLE_BANSHEE default 0x1 if BOARD_GOOGLE_KINOX default 0x0 if BOARD_GOOGLE_CRAASK + default 0x1 if BOARD_GOOGLE_CROTA config DRIVER_TPM_I2C_ADDR hex 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb3ce6c2faf857c8f5d789af395e315caea4102 Gerrit-Change-Number: 63617 Gerrit-PatchSet: 7 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2022