coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya: Disable PCH USB2 phy power gating for felwinter
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63294 ) Change subject: mb/google/brya: Disable PCH USB2 phy power gating for felwinter ...................................................................... mb/google/brya: Disable PCH USB2 phy power gating for felwinter The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for felwinter board. Please refer Intel doc#723158 for more information. BUG=b:221461379, b:226020977 TEST=Verify the build for felwinter board Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/felwinter/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb index a89ad95..d2ecf4a 100644 --- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb +++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb @@ -44,6 +44,10 @@ [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, }" + # As per Intel Advisory doc#723158, the change is required to prevent possible + # display flickering issue. + register "usb2_phy_sus_pg_disable" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/63294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb Gerrit-Change-Number: 63294 Gerrit-PatchSet: 10 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: update type-c setting in overridetree
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63570 ) Change subject: mb/google/brask/variants/moli: update type-c setting in overridetree ...................................................................... mb/google/brask/variants/moli: update type-c setting in overridetree Add conn1 for pch_espi and add type-c port2 for pmc_mux. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63570 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index e9bc846..eb13b06 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -113,6 +113,7 @@ device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] + use conn1 as mux_conn[1] device pnp 0c09.0 on end end end @@ -124,6 +125,11 @@ use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end end end end 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd7b761496a110f34838abb0fd408b37d390ba2 Gerrit-Change-Number: 63570 Gerrit-PatchSet: 9 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: add delay time to rtd3-cold
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63544 ) Change subject: mb/google/brask/variants/moli: add delay time to rtd3-cold ...................................................................... mb/google/brask/variants/moli: add delay time to rtd3-cold This CL adds the delay time 50 ms and 20 ms into the RTD3 sequence, the reason is that the rise and fall times of each signal may differ by board, and so those board-specific delays must be taken into account when power sequencing. We checked power on sequence requires enable pin prior to reset pin, so added delay to meet the sequence. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:228907551 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63544 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 5d17976..e9bc846 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -100,6 +100,8 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "srcclk_pin" = "1" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end # Enable PCIe-to-eMMC bridge PCIE 12 using clk 1 register "pch_pcie_rp[PCH_RP(12)]" = "{ 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63544 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idecb1c89655c9b8b720c3c65efc77e06e6a8b300 Gerrit-Change-Number: 63544 Gerrit-PatchSet: 11 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/Kconfig: Remove SOC_AMD_COMMON_BLOCK_UCODE_SIZE
by Fred Reitberger (Code Review) 19 Apr '22

19 Apr '22

Fred Reitberger has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63590 ) Change subject: soc/amd/*/Kconfig: Remove SOC_AMD_COMMON_BLOCK_UCODE_SIZE ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/63590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e94580ea038f1b6f866f08798e1edd8597ba5c9 Gerrit-Change-Number: 63590 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brask/variants/moli: remove i2c1 in overridetree
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63545 ) Change subject: mb/google/brask/variants/moli: remove i2c1 in overridetree ...................................................................... mb/google/brask/variants/moli: remove i2c1 in overridetree Remove i2c1 because brask devicetree is already has it. BUG=b:220814038 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/moli/overridetree.cb 1 file changed, 1 insertion(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index 9d443ed..5d17976 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -219,14 +219,7 @@ end end end - end #USB2 and USB3 Port - device ref i2c1 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end # tpm + end # USB2 and USB3 Port end end 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic782e1c6434ac57bdf65b3d9f4219bdf32d25b9e Gerrit-Change-Number: 63545 Gerrit-PatchSet: 8 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Configure Pen Detect device
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63633 ) Change subject: mb/google/skyrim: Configure Pen Detect device ...................................................................... mb/google/skyrim: Configure Pen Detect device Enable pen garage. Pen detect is active low. BUG=b:229168203 TEST:Build and boot to OS in skyrim. Evtest work as expected Input driver version is 1.0.1 Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100 Input device name: "PRP0001:00" Supported events: Event type 0 (EV_SYN) Event type 5 (EV_SW) Event code 15 (SW_PEN_INSERTED) state 1 Properties: Testing ... (interrupt to exit) Event: time 1649922170.578779, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0 Event: time 1649922170.578779, -------------- SYN_REPORT ------------ Event: time 1649922172.070740, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63633 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb 2 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index a32a2cb..37091ab 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -18,6 +18,7 @@ def_bool y select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_WIFI_GENERIC diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 02b8c1c..3b33a5d 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -84,5 +84,17 @@ register "hid_desc_reg_offset" = "0x01" device i2c 5d on end end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPIO_3)" + register "key.dev_name" = ""EJCT"" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + register "key.debounce_interval" = "100" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + device generic 0 on end + end end # I2C1 end # chip soc/amd/sabrina 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63633 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bb07af6aebdc355a73148d8be79b1014147f61d Gerrit-Change-Number: 63633 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Add Goodix touchscreen
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63573 ) Change subject: mb/google/skyrim: Add Goodix touchscreen ...................................................................... mb/google/skyrim: Add Goodix touchscreen Add Goodix touchscreen according to the Programming Guide Rev.0.7 BUG=b:228907558 TEST=local build and tested with Goodix touch screen Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63573 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/skyrim/variants/baseboard/gpio.c M src/mainboard/google/skyrim/variants/skyrim/overridetree.cb 2 files changed, 23 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/baseboard/gpio.c b/src/mainboard/google/skyrim/variants/baseboard/gpio.c index a262347..6ff2906 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/gpio.c +++ b/src/mainboard/google/skyrim/variants/baseboard/gpio.c @@ -58,8 +58,8 @@ /* SD_AUX_RESET_L */ PAD_GPO(GPIO_27, HIGH), /* GPIO_28: Not available */ - /* EN_PP3300_TCHSCR */ - PAD_GPO(GPIO_29, HIGH), + /* TCHSCR_INT_ODL */ + PAD_GPI(GPIO_29, PULL_NONE), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* Unused */ @@ -113,8 +113,8 @@ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE), /* SOC_FPMCU_BOOT0 */ PAD_GPO(GPIO_130, LOW), - /* TCHSCR_INT_ODL */ - PAD_GPI(GPIO_131, PULL_NONE), + /* EN_PP3300_TCHSCR */ + PAD_GPO(GPIO_131, LOW), /* TCHSCR_RESET_L */ PAD_GPO(GPIO_136, LOW), /* SOC_BIOS_WP_L */ diff --git a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb index 0b965eb5..02b8c1c 100644 --- a/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/skyrim/overridetree.cb @@ -66,4 +66,23 @@ device i2c 15 on end end end # I2C0 + device ref i2c_1 on + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_29)" + register "generic.probed" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_131)" + register "generic.enable_delay_ms" = "10" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_136)" + register "generic.reset_off_delay_ms" = "1" + register "generic.reset_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_76)" + register "generic.stop_delay_ms" = "180" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + end # I2C1 end # chip soc/amd/sabrina -- To view, visit https://review.coreboot.org/c/coreboot/+/63573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35dd3ca76e9e0f17508bef46c90b53b4be5d0033 Gerrit-Change-Number: 63573 Gerrit-PatchSet: 4 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Jon Murphy <jpmurphy(a)google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent
by Lean Sheng Tan (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, Arthur Heymans, Eric Lai. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63518 ) Change subject: soc/intel/common/{sa, adl}: Add `finalize` operation for systemagent ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599 Gerrit-Change-Number: 63518 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 13:06:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brask: fix boot beep
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63645 ) Change subject: mb/google/brask: fix boot beep ...................................................................... mb/google/brask: fix boot beep Fix the issue that can't hear the boot beep at dev screen. GPP_B14 is used for PWM_PP3300_BUZZER and it should set to GPO. Modify GPP_B14 from PAD_CFG_NF_LOCK to PAD_CFG_GPO_LOCK. BUG=b:229345416 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot and verify if the buzzer beeps. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63645 Reviewed-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/baseboard/brask/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Frank Wu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index 93f5393..e81bd05 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -80,7 +80,7 @@ /* B13 : PLTRST# ==> PLT_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* B14 : SPKR ==> PWM_PP3300_BUZZER */ - PAD_CFG_NF_LOCK(GPP_B14, NONE, NF1, LOCK_CONFIG), + PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG), /* B15 : TIME_SYNC0 ==> TP159 */ PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I601735ab20974cd992ca5dd6dbaca1517a395aa2 Gerrit-Change-Number: 63645 Gerrit-PatchSet: 6 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brask/variants/moli: Pick VBT based on FW_CONFIG
by Felix Held (Code Review) 19 Apr '22

19 Apr '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63604 ) Change subject: mb/google/brask/variants/moli: Pick VBT based on FW_CONFIG ...................................................................... mb/google/brask/variants/moli: Pick VBT based on FW_CONFIG Pick specific VBTs for HDMI, DP, and ABSENT according to FW_CONFIG. BUG=b:220241277 TEST=emerge-brask coreboot. Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Change-Id: Icc8fbef1467605505459fce264697f670591c81e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63604 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/moli/ramstage.c 1 file changed, 11 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/moli/ramstage.c b/src/mainboard/google/brya/variants/moli/ramstage.c index 5690156..af563ba 100644 --- a/src/mainboard/google/brya/variants/moli/ramstage.c +++ b/src/mainboard/google/brya/variants/moli/ramstage.c @@ -5,7 +5,9 @@ #include <device/device.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <drivers/intel/gma/opregion.h> #include <ec/google/chromeec/ec.h> +#include <fw_config.h> #include <intelblocks/power_limit.h> const struct cpu_power_limits limits[] = { @@ -30,6 +32,15 @@ .bj_volts_mv = 19500 }; +const char *mainboard_vbt_filename(void) +{ + if (fw_config_probe(FW_CONFIG(DB_OPT, OPT_HDMI))) + return "vbt-moli_HDMI.bin"; + else if (fw_config_probe(FW_CONFIG(DB_OPT, OPT_DP))) + return "vbt-moli_DP.bin"; + return "vbt-moli.bin"; +} + void variant_devtree_update(void) { size_t total_entries = ARRAY_SIZE(limits); -- To view, visit https://review.coreboot.org/c/coreboot/+/63604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc8fbef1467605505459fce264697f670591c81e Gerrit-Change-Number: 63604 Gerrit-PatchSet: 14 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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