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Change subject: util/cbfstool/linux_trampoline: Use payload calling argument
......................................................................
Patch Set 2: Code-Review+1
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Change subject: apple/macbook21: configure the clockgen and add C3 CPU state
......................................................................
Patch Set 6:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63587/comment/7a8f55c1_d9f8e412
PS6, Line 11:
Please extend the commit message, describing why the overridetree is needed for example, and which models have what clockgen, and so on.
File src/mainboard/apple/macbook21/cstates.c:
https://review.coreboot.org/c/coreboot/+/63587/comment/ec12b9db_fc463a5b
PS4, Line 34: .latency = 17,
> That latency value works perfectly fine. […]
Only because you do not experience any problems with your use cases, this does not have to be the correct value, does it?
File src/mainboard/apple/macbook21/cstates.c:
https://review.coreboot.org/c/coreboot/+/63587/comment/570d484b_709275de
PS6, Line 32: #if !CONFIG(BOARD_APPLE_IMAC52)
Preprocessor statement are not indented to my knowledge.
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Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/brya0/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63709/comment/de0359a1_428f0bb3
PS1, Line 70: .speed = I2C_SPEED_FAST,
miss i2c tuning?
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Change subject: util/cbfstool/linux_trampoline: Use payload calling argument
......................................................................
Patch Set 2:
(1 comment)
File util/cbfstool/linux_trampoline.S:
https://review.coreboot.org/c/coreboot/+/63611/comment/59bee408_61fd1813
PS2, Line 5: * IT SHOULDN'T USE THE STACK
this assumption is now broken...
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Change subject: mb/google/guybrush/var/dewatt: Update APU STT setting
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/block/smbus/smbus.c:
https://review.coreboot.org/c/coreboot/+/63640/comment/4f96f370_d1b209ec
PS4, Line 88: smbus_final
> Suggestion: […]
Ack
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Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63640
to look at the new patch set (#5).
Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus
......................................................................
soc/intel/common/smbus: Add `finalize` operation for smbus
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Post PCI Enumeration.
The smbus `.final` operation ensures locking the TCO register when
coreboot decides to skip FspNotifyApi() calls.
BUG=b:211954778
TEST=Able to build google/brya with these changes and coreboot log with
this code change as below with ADL SoC skip calling into FspNotifyAPIs:
[INFO ] Finalize devices...
[DEBUG] PCI: 00:1f.4 final
> localhost ~ # lspci -xxx | less
00:1f.4 Intel Corporation Alder Lake PCH-P SMBus Host Controller
(rev 01)
Offset 8, Bit 12 a.k.a TCO Lock bit is set (meaning locked).
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie945680049514e6c5d797790a381a6946e836926
---
M src/soc/intel/common/block/smbus/smbus.c
1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63640/5
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