coreboot-gerrit April 2022

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Change in coreboot[master]: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Kangheui Won, harsha.b.r(a)intel.com, Paul Menzel, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Ronak Kanabar, Usha P. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62323 ) Change subject: soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... Patch Set 7: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62323/comment/3070aff1_0a7d405b PS7, Line 26: which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY sorry! who is expecting data using v1 structure ? FSP? Do that mean, ADL-Ncpu (Atoms) doesn't support v2 hence, better to pass v1 data structure which is unified. https://review.coreboot.org/c/coreboot/+/62323/comment/e7129454_ada427f8 PS7, Line 23: FSP queries coreboot MP services to get CPU topology data which uses : structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or : CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since coreboot returns V2 data in : structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there : is hang observed on ADL_N CPUs. : this part is not very clear to me. This issue is seen with ADL-N and not ADL-P (please correct me if wrong) then, FSP is same between ADL-P and ADL-N, in that case why expectation in FSP would be different compared to ADL-P? https://review.coreboot.org/c/coreboot/+/62323/comment/bdb2c4bc_c0e8bc65 PS7, Line 33: Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 : Files: : MdePkg/Include/Protocol/MpService.h#L182 : UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 : UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 I don't think, we have any guideline that says, "write the code based on EDKII" 😊 Not sure if pointing to EDKII code is helpful here? https://review.coreboot.org/c/coreboot/+/62323/comment/1b479fc9_164c038f PS7, Line 41: ADL-N RVP where is testing data about ADL-P? you are changing behaviour for ADL-P as well. Did you see any issue with Brya devices ? https://review.coreboot.org/c/coreboot/+/62323/comment/03f08eb4_3857c253 PS7, Line 42: (no hang) IMO, what is the root-cause is still missing. -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:23:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib/coreboot_table.c: Make sure entries are 32 bit aligned
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/63710 ) Change subject: lib/coreboot_table.c: Make sure entries are 32 bit aligned ...................................................................... Abandoned structs are always aligned to the largest size of an entry. So this is not an issue. -- To view, visit https://review.coreboot.org/c/coreboot/+/63710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Gerrit-Change-Number: 63710 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/brya/var/corta: enable CPU PCIe VGPIO
by Scott Chao (Code Review) 19 Apr '22

19 Apr '22

Scott Chao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63713 ) Change subject: mb/google/brya/var/corta: enable CPU PCIe VGPIO ...................................................................... mb/google/brya/var/corta: enable CPU PCIe VGPIO - enable CPU PCIe VGPIO for PEG60. - enable GPP_C3/ GPP_C4 native function. - set unused GPIO to NC BUG=b:229584785 BRANCH=none TEST=build and boot into kernel Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964 --- M src/mainboard/google/brya/variants/crota/gpio.c 1 file changed, 37 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/63713/1 diff --git a/src/mainboard/google/brya/variants/crota/gpio.c b/src/mainboard/google/brya/variants/crota/gpio.c index ad13426..ee8ee19 100644 --- a/src/mainboard/google/brya/variants/crota/gpio.c +++ b/src/mainboard/google/brya/variants/crota/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), /* A19 : DDSP_HPD1 ==> NC */ PAD_NC(GPP_A19, NONE), /* A20 : DDSP_HPD2 ==> NC */ @@ -16,17 +18,22 @@ /* A22 : DDPC_CTRLDATA ==> NC */ PAD_NC(GPP_A22, NONE), - /* C3 : SML0CLK ==> SML0_SMBCLK */ - PAD_CFG_GPO(GPP_C3, 0, DEEP), - /* C4 : SML0DATA ==> SML0_SMBDATA */ - PAD_CFG_GPO(GPP_C4, 0, DEEP), + /* B2 : VRALERT# ==> NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : PROC_GP2 ==> NC */ + PAD_NC(GPP_B3, NONE), + /* B15 : TIME_SYNC0 ==> NC */ + PAD_NC(GPP_B15, NONE), + + /* C3 : GPP_C3 ==> SML0_SMBCLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : GPP_C4 ==> SML0_SMBDATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* D3 : ISH_GP3 ==> NC */ PAD_NC(GPP_D3, NONE), /* D5 : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - /* D6 : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D13 : ISH_UART0_RXD ==> NC */ PAD_NC(GPP_D13, NONE), /* D14 : ISH_UART0_TXD ==> NC */ @@ -51,6 +58,8 @@ /* E23 : DDPA_CTRLDATA ==> NC */ PAD_NC(GPP_E23, NONE), + /* F19 : SRCCLKREQ6# ==> NC */ + PAD_NC(GPP_F19, NONE), /* F20 : EXT_PWR_GATE# ==> NC */ PAD_NC(GPP_F20, NONE), @@ -139,6 +148,28 @@ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; static const struct pad_config romstage_gpio_table[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964 Gerrit-Change-Number: 63713 Gerrit-PatchSet: 1 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Implement PCH lock down configuration
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63692 ) Change subject: soc/intel/alderlake: Implement PCH lock down configuration ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/lockdown.c: https://review.coreboot.org/c/coreboot/+/63692/comment/493ab53e_f1759afb PS2, Line 17: /* Trap status Register */ > What does this comment mean? my bad, fixed now. -- To view, visit https://review.coreboot.org/c/coreboot/+/63692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c Gerrit-Change-Number: 63692 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Implement PMC feature lock
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Arthur Heymans, Nick Vaccaro, Eric Lai, Lean Sheng Tan, Werner Zeh. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63691 ) Change subject: soc/intel/alderlake: Implement PMC feature lock ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/include/soc/pmc.h: https://review.coreboot.org/c/coreboot/+/63691/comment/00dec7a4_811e0019 PS2, Line 80: #define PM_CFG_DBG_MODE_LOCK (1 << 27) > nit: one tab missing Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29178bdd9a94a24ca7056eb7377625f41a43c33c Gerrit-Change-Number: 63691 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:08:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/corta: enable boot from SSD/ eMMC
by Scott Chao (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Eric Lai. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63683 ) Change subject: mb/google/brya/var/corta: enable boot from SSD/ eMMC ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63683/comment/4b3dba28_5a837291 PS4, Line 14: > `boot` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Gerrit-Change-Number: 63683 Gerrit-PatchSet: 6 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:04:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/corta: enable boot from SSD/ eMMC
by Scott Chao (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Eric Lai. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63683 to look at the new patch set (#6). Change subject: mb/google/brya/var/corta: enable boot from SSD/ eMMC ...................................................................... mb/google/brya/var/corta: enable boot from SSD/ eMMC - Fix eMMC reset/ enable GPIO pins. - Fix clk_req and clk_src BUG=b:229437061 BRANCH=none TEST=build and boot without error Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63683/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/63683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id16e292ec7557d1780516a267bd752014d98e463 Gerrit-Change-Number: 63683 Gerrit-PatchSet: 6 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/var/corta: limit dram speed at 4800
by Scott Chao (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Eric Lai. Scott Chao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63682 ) Change subject: mb/google/brya/var/corta: limit dram speed at 4800 ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63682/comment/c4a0f705_22d5e8b9 PS1, Line 8: > Can we add the reason why here? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 11:03:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/corta: limit dram speed at 4800
by Scott Chao (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Eric Lai. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63682 to look at the new patch set (#3). Change subject: mb/google/brya/var/corta: limit dram speed at 4800 ...................................................................... mb/google/brya/var/corta: limit dram speed at 4800 For tyep-3 PCB board, the dram speed must not higher than 4800. BUG=b:229549930 BRANCH=none TEST=build and pass memory training Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Change-Id: I38f0006d478702afb382d30338f20b46641964ef --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63682/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38f0006d478702afb382d30338f20b46641964ef Gerrit-Change-Number: 63682 Gerrit-PatchSet: 3 Gerrit-Owner: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib/coreboot_table.c: Make sure entries are 32 bit aligned
by Arthur Heymans (Code Review) 19 Apr '22

19 Apr '22

Arthur Heymans has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/63710 ) Change subject: lib/coreboot_table.c: Make sure entries are 32 bit aligned ...................................................................... lib/coreboot_table.c: Make sure entries are 32 bit aligned Some entries like lb_framebuffer have unaligned sizes. Each entry is added right above the previous one so the entry after unaligned entries would result in unaligned pointer access, which is invalid on some CPU arch. Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/coreboot_table.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63710/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I278245894ef2f23c4f058abb8467e7af41cadcbd Gerrit-Change-Number: 63710 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2022