coreboot-gerrit April 2022

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Change in coreboot[master]: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
by Frank Wu (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63709 ) Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/63709/comment/80afe357_c6f2f76b PS1, Line 64: #| I2C2 | | Please add devices based on the overridetree.cb and the schematic. -- To view, visit https://review.coreboot.org/c/coreboot/+/63709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Gerrit-Change-Number: 63709 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:48:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct genera...
by Christian Walter (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Martin Roth, Arthur Heymans. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63350 ) Change subject: Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct generation ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7067ff144d38c1ff058825819419b2a2e7801e17 Gerrit-Change-Number: 63350 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:44:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct genera...
by Lean Sheng Tan (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Martin Roth, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63350 ) Change subject: Makefile.inc: Add fmap_config.h as a dependency to cbfs-struct generation ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7067ff144d38c1ff058825819419b2a2e7801e17 Gerrit-Change-Number: 63350 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:42:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
by Frank Wu (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Amanda Hwang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63709 ) Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Gerrit-Change-Number: 63709 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:40:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus
by Amanda Hwang (Code Review) 19 Apr '22

19 Apr '22

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63709 ) Change subject: mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus ...................................................................... mb/google/brya/var/brya0: Swap TPM and touchscreen I2C bus Based on the latest schematic, exchange I2C port for TPM/touchscreen. TPM: I2C3 -> I2C1 Touchscreen: I2C1 -> I2C3 BUG=b:202671753 TEST=emerge-brya coreboot Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/brya0/gpio.c M src/mainboard/google/brya/variants/brya0/overridetree.cb 3 files changed, 143 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/63709/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 0fafc2f..fb2cf05 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -95,7 +95,7 @@ config DRIVER_TPM_I2C_BUS hex - default 0x3 if BOARD_GOOGLE_BRYA0 + default 0x1 if BOARD_GOOGLE_BRYA0 default 0x3 if BOARD_GOOGLE_BRYA4ES default 0x1 if BOARD_GOOGLE_BRASK default 0x1 if BOARD_GOOGLE_PRIMUS diff --git a/src/mainboard/google/brya/variants/brya0/gpio.c b/src/mainboard/google/brya/variants/brya0/gpio.c index 4cf99df..606c123 100644 --- a/src/mainboard/google/brya/variants/brya0/gpio.c +++ b/src/mainboard/google/brya/variants/brya0/gpio.c @@ -117,6 +117,51 @@ PAD_NC(GPP_H13, UP_20K), }; +/* Early pad configuration in bootblock for board id 4 */ +static const struct pad_config early_gpio_table_id4[] = { + /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_A12, 1, DEEP), + /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* H6 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* + * D1 : ISH_GP1 ==> FP_RST_ODL + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + PAD_CFG_GPO(GPP_D1, 0, DEEP), + /* D2 : ISH_GP2 ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + /* E0 : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E0, 0, DEEP), + /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_E13, NONE, DEEP), + /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */ + PAD_CFG_GPO(GPP_E16, 0, DEEP), + /* E15 : RSVD_TP ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H13 : I2C7_SCL ==> EN_PP3300_SD */ + PAD_NC(GPP_H13, UP_20K), +}; + static const struct pad_config romstage_gpio_table[] = { /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), @@ -142,6 +187,9 @@ if (id == BOARD_ID_UNKNOWN || id < 2) { *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; + } else if (id >= 4) { + *num = ARRAY_SIZE(early_gpio_table_id4); + return early_gpio_table_id4; } *num = ARRAY_SIZE(early_gpio_table_id2); diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb index fd8224c..37062f7 100644 --- a/src/mainboard/google/brya/variants/brya0/overridetree.cb +++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb @@ -52,6 +52,38 @@ .configure_ext_fivr = 1, }" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | | + #| I2C3 | TouchScreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -359,62 +391,12 @@ end end #I2C0 device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN9050"" - register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "300" - register "generic.reset_off_delay_ms" = "1" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "6" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "12" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_off_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 0x5d on end - end - chip drivers/i2c/hid - register "generic.hid" = ""SIS9815"" - register "generic.desc" = ""SIS Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_delay_ms" = "100" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "7" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x00" - device i2c 5c on end - end - end + end #I2C1 device ref i2c2 on chip drivers/i2c/sx9324 register "desc" = ""SAR1 Proximity Sensor"" @@ -584,14 +566,64 @@ probe HPS HPS_PRESENT end end - end + end #I2C2 device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end end - end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "12" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x5d on end + end + chip drivers/i2c/hid + register "generic.hid" = ""SIS9815"" + register "generic.desc" = ""SIS Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_delay_ms" = "100" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "7" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x00" + device i2c 5c on end + end + end #I2C3 device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" @@ -601,7 +633,7 @@ register "probed" = "1" device i2c 15 on end end - end + end #I2C5 device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" -- To view, visit https://review.coreboot.org/c/coreboot/+/63709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa6235869f34e0038a8ecad33d59654626cf7815 Gerrit-Change-Number: 63709 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Ronak Kanabar (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P. Hello V Sowmya, build bot (Jenkins), Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62323 to look at the new patch set (#6). Change subject: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY(0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2(0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY(0x0B) returns data related to number of threads, core and package, CPUID_EXTENDED_CPU_TOPOLOGY_V2(0x1F) provide more granular information regarding Die, package etc. Coreboot uses V2 to inorder to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since Coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To Solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and didn't observe hang while booting. Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62323/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Ronak Kanabar (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P. Hello V Sowmya, build bot (Jenkins), Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62323 to look at the new patch set (#5). Change subject: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 In x86 processor as per Software Developer's manual there are 2 ways to get CPU topology by querying the processor. BIOS can use CPUID instruction using CPUID_EXTENDED_CPU_TOPOLOGY(0x0B) as input or CPUID_EXTENDED_CPU_TOPOLOGY_V2(0x1F) as an input. Both will return valid CPU topology data. While CPUID_EXTENDED_CPU_TOPOLOGY(0x0B) returns data related to number of threads, core and package, V2(0x1F) provide more granular information regarding Die, package etc. Coreboot uses V2 to inorder to query and return CPU topology data as of now since that's the highest instruction of CPUID which is supported, there is a mismatch in the way FSP processes the data. FSP queries coreboot MP services to get CPU topology data which uses structure which is either compatible with CPUID_EXTENDED_CPU_TOPOLOGY or CPUID_EXTENDED_CPU_TOPOLOGY_V2. Since Coreboot returns V2 data in structure which is expecting data for CPUID_EXTENDED_CPU_TOPOLOGY, there is hang observed on ADL_N CPUs. To Solve this problem coreboot should assign CPUID_EXTENDED_CPU_TOPOLOGY data to processor_info_buffer->Location structure so remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 Ref EDK2 code: https://github.com/tianocore/edk2/tree/edk2-stable202202 Files: MdePkg/Include/Protocol/MpService.h#L182 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2127 UefiCpuPkg/Library/MpInitLib/MpLib.c#L2120 Ref doc: Software Developer’s Manual volume 3 CH 8.9 BUG=b:220652104 TEST=Build and boot ADL-N RVP with debug FSP and verify CPU topology value and didn't Observe hang while booting. Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62323/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 5 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2
by Ronak Kanabar (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: V Sowmya, Saurabh Mishra, Subrata Banik, harsha.b.r(a)intel.com, Kangheui Won, Reka Norman, Rizwan Qureshi, Krishna P Bhat D, Usha P. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62323 ) Change subject: soc/intel/common : Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2 ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/62323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e6832fb03fcc59d33df0ba1664019727185d10a Gerrit-Change-Number: 62323 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: harsha.b.r(a)intel.com Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: harsha.b.r(a)intel.com Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 09:20:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/osiris: Generate SPD ID for supported parts
by David Wu (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Ren Kuo, Tim Wawrzynczak, Nick Vaccaro. David Wu has removed EricR Lai from this change. ( https://review.coreboot.org/c/coreboot/+/63706 ) Change subject: mb/google/brya/var/osiris: Generate SPD ID for supported parts ...................................................................... Removed reviewer EricR Lai. -- To view, visit https://review.coreboot.org/c/coreboot/+/63706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbdce203afd282cef9fcd7aebbace69d19fbbf1 Gerrit-Change-Number: 63706 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: Kconfig: Add an option to ommit a cbfs master header
by Christian Walter (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Julius Werner, Arthur Heymans. Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63378 ) Change subject: Kconfig: Add an option to ommit a cbfs master header ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d5b32412db40df48c0ed4dd6216bdd9cb955e2 Gerrit-Change-Number: 63378 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 19 Apr 2022 08:34:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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