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Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63630/comment/6d62be91_e3249100
PS4, Line 94: static void lpc_lockdown_config(int chipset_lockdown)
> Hmmm, how do the LPC "write protect" bits work, given that the SPI PCI device also has equivalent bits? Do they do anything?
It's mostly for FWH (firmware HUB) LPC interface.
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55455
to look at the new patch set (#26).
Change subject: amdfwtool: Use command line option use-combo to decide if use combo
......................................................................
amdfwtool: Use command line option use-combo to decide if use combo
The macro PSP_COMBO is removed and instead use the flag use_combo. As
long as this flag is false, the amdfwtool behaves the same way as the
macro does.
Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 18 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/55455/26
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Change subject: soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration)
......................................................................
Patch Set 2: Code-Review+1
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Change subject: soc/intel/alderlake: Implement PCH lock down configuration
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63692/comment/3a01b6aa_29e11590
PS2, Line 17: /* Trap status Register */
What does this comment mean?
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Change subject: soc/intel/alderlake: Implement PMC feature lock
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/63691/comment/a7646864_0fd26ec8
PS2, Line 80: #define PM_CFG_DBG_MODE_LOCK (1 << 27)
nit: one tab missing
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Change subject: soc/intel/alderlake: Implement PMC soft strap interface lock
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Change subject: soc/intel/alderlake: Implement PMC static function lock
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Change subject: soc/intel/cannonlake: Drop unused LPC BIOS Control macro
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Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus
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Change subject: soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63630/comment/76331b48_d59c4904
PS4, Line 14: configuration register offset 0xDC bits BILD and LE are set.
Could you please test what happens after setting the WPD bit from the OS? For example, using setpci:
sudo setpci -s 0:1f.0 0xdc.b=0x0a
I ask because I had troubles with the SPI PCI device where the SMI handler would fail to clear the SMI source, and the system would hang (it would be stuck in a SMI storm). See CB:50754 for the fix. I don't think this issue can happen with LPC, but I'd appreciate if you could test just to make sure.
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63630/comment/ca501f06_f0ce657e
PS4, Line 94: static void lpc_lockdown_config(int chipset_lockdown)
Hmmm, how do the LPC "write protect" bits work, given that the SPI PCI device also has equivalent bits? Do they do anything?
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