coreboot-gerrit April 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63624 ) Change subject: soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress ...................................................................... soc/intel/cmn/fast_spi: Add API to check if SPI Cycle In Progress This patch creates a helper function to check if any SPI transaction is pending. As per Intel PCH BIOS spec section 3.6 Flash Security Recommendation, it's important to ensure there is no pending SPI transaction before setting SPI lock bits. BUG=b:211954778 TEST=Able to build google/brya with this patch and no error msg seen due to `SPI transaction is pending`. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63624 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/fast_spi/fast_spi_flash.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index 269db63..2bc7cf1 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -161,6 +161,18 @@ return wait_for_hwseq_xfer(ctx, flash_addr); } +int fast_spi_cycle_in_progress(void) +{ + BOILERPLATE_CREATE_CTX(ctx); + + int ret = wait_for_hwseq_spi_cycle_complete(ctx); + if (ret != SUCCESS) + printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) due to prior" + " operation is pending\n", SPIBAR_HWSEQ_XFER_TIMEOUT_MS); + + return ret; +} + /* * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and * that the operation does not cross page boundary. diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index a903ea83..eb3f2aa 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -5,6 +5,8 @@ #include <types.h> +/* Check if SPI transaction is pending */ +int fast_spi_cycle_in_progress(void); /* * Disable the BIOS write protect and Enable Prefetching and Caching. */ 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63624 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd3f67ae60bfcb3610cd0950b057da97ff74b5b9 Gerrit-Change-Number: 63624 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPC
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63629 ) Change subject: soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPC ...................................................................... soc/intel/cmn/lpc: Fix typo from FAST_SPIBAR to LPC BUG=b:211954778 TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib8cc4b8d13b61e3935f2050d25ce0278162c91c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63629 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/lpc/lpc_lib.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 2bd9858..a44c2da 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -152,7 +152,7 @@ } /* - * Set FAST_SPIBAR BIOS Control register based on input bit field. + * Set LPC BIOS Control register based on input bit field. */ static void lpc_set_bios_control_reg(uint8_t bios_cntl_bit) { 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8cc4b8d13b61e3935f2050d25ce0278162c91c4 Gerrit-Change-Number: 63629 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6%
by Robert Chen (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Paul Menzel. Robert Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63440 ) Change subject: mb/google/brya/var/vell: increase RFI Spread Spectrum to 6% ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: Hi Tim, please kindly review this commit -- To view, visit https://review.coreboot.org/c/coreboot/+/63440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cdca8f51ad18f4ab03e4e6c744b60da68263ce2 Gerrit-Change-Number: 63440 Gerrit-PatchSet: 9 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 05:45:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cmn/fast_spi: Use tab instead space
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63623 ) Change subject: soc/intel/cmn/fast_spi: Use tab instead space ...................................................................... soc/intel/cmn/fast_spi: Use tab instead space This patch converts whitespace into tabs to maintain the uniformity across the fast_spi_def.h file. BUG=b:211954778 TEST=Able to build google/brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I56bcd263c6a5c0036e459926a25538e3448fbce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63623 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/common/block/fast_spi/fast_spi_def.h 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_def.h b/src/soc/intel/common/block/fast_spi/fast_spi_def.h index 353c89f..f28865d 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_def.h +++ b/src/soc/intel/common/block/fast_spi/fast_spi_def.h @@ -140,9 +140,9 @@ #define SPIBAR_PTINX_IDX_MASK 0xffc /* Register Offsets of BIOS Flash Program Registers */ -#define SPIBAR_RESET_LOCK 0xf0 -#define SPIBAR_RESET_CTRL 0xf4 -#define SPIBAR_RESET_DATA 0xf8 +#define SPIBAR_RESET_LOCK 0xf0 +#define SPIBAR_RESET_CTRL 0xf4 +#define SPIBAR_RESET_DATA 0xf8 /* Programmable values of Bit0 (SSL) of Set STRAP MSG LOCK (0xF0) Register */ #define SPIBAR_RESET_LOCK_DISABLE 0 /* Set_Strap Lock(SSL) Bit 0 = 0 */ 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56bcd263c6a5c0036e459926a25538e3448fbce6 Gerrit-Change-Number: 63623 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/fast_spi: Use `need_restore_mtrr()` to clear temp MTRR
by Subrata Banik (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Nick Vaccaro, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63492 ) Change subject: soc/intel/fast_spi: Use `need_restore_mtrr()` to clear temp MTRR ...................................................................... Patch Set 2: (1 comment) File src/cpu/x86/mtrr/mtrrlib.c: https://review.coreboot.org/c/coreboot/+/63492/comment/6ab6e3a2_27b38eb6 PS1, Line 52: /* Need to restore mtrr later using remove_temp_solution. */ : if (ENV_RAMSTAGE) : need_restore_mtrr(); > > Ack > > @Arthur, can you please take a look into this Temp solution, till we figure out how to manage ramstage Temp MTRR solution in better way using CB:63550 or CB:63555. Ping! -- To view, visit https://review.coreboot.org/c/coreboot/+/63492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67fd36080b318ace53f3e34da53d747f9a3aa400 Gerrit-Change-Number: 63492 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 05:44:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP
by Kangheui Won (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Daniil Lunev, Subrata Banik, Wonkyu Kim, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Meera Ravindranath, Angel Pons, Patrick Rudolph, Gwendal Grignou. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62662 ) Change subject: mb/intel/adlrvp: Enable UFS and ISH for ADL-N RVP ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If15bcaffc8fd3bbbe4b181820993ab2d882bbbe1 Gerrit-Change-Number: 62662 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniil Lunev <dlunev(a)chromium.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Daniil Lunev <dlunev(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 05:13:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: docs/coding_style: Clarify use of GCC extensions
by David Hendricks (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Arthur Heymans, Hung-Te Lin, Nico Huber, Paul Menzel, Julius Werner. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63660 ) Change subject: docs/coding_style: Clarify use of GCC extensions ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Is there value in a section on what to do if a developer encounters a GCC extension that their compiler of choice doesn't support? "Wrap your code in a preprocessor guard and let us know via the mailing list if it gets too messy" or something to that effect? I'm fine with saying that GCC is the officially-supported compiler of coreboot, but predicting the future is hard and there might be good reason to use another compiler in certain cases. -- To view, visit https://review.coreboot.org/c/coreboot/+/63660 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11 Gerrit-Change-Number: 63660 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 19 Apr 2022 05:11:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Add sa_get_mchbar_base api
by Wonkyu Kim (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons. Hello build bot (Jenkins), Subrata Banik, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63615 to look at the new patch set (#7). Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api ...................................................................... intel/common/../systemagent: Add sa_get_mchbar_base api Implement sa_get_mchbar_base api to get mchbar base address. This api reads mchbar base address from pci config space if MCHBAR is enabled and program MCHBAR base address and enable MCH BAR if MCHBAR is not enabled. This api will be used in IOC driver for new SOC like Meteor Lake. Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb --- M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/systemagent_early.c 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63615/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 7 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Implement IOC driver
by Wonkyu Kim (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Jamie Ryu, Subrata Banik, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Tim Wawrzynczak, Angel Pons, Nick Vaccaro. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63198 ) Change subject: soc/intel/common: Implement IOC driver ...................................................................... Patch Set 19: (4 comments) File src/soc/intel/common/block/include/intelblocks/systemagent.h: https://review.coreboot.org/c/coreboot/+/63198/comment/a2085ca5_a791cfa5 PS18, Line 56: sa_get_mchbar_base > suggestion: to submit as a separate CL. Ack File src/soc/intel/common/block/ioc/ioc.c: https://review.coreboot.org/c/coreboot/+/63198/comment/c87b0af6_16ceab8d PS18, Line 16: > remove this ? Ack https://review.coreboot.org/c/coreboot/+/63198/comment/2030715f_69aac47f PS18, Line 23: > same Ack File src/soc/intel/common/block/systemagent/systemagent_early.c: https://review.coreboot.org/c/coreboot/+/63198/comment/20e74d89_92e6ccac PS18, Line 83: sa_get_mchbar_base > may be, you can submit this as separator CL as a base, then it would be easy. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/63198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I768027c2ca78310c03845f70f17df19dc8cd0982 Gerrit-Change-Number: 63198 Gerrit-PatchSet: 19 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 04:37:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/common/../systemagent: Add sa_get_mchbar_base api
by Wonkyu Kim (Code Review) 19 Apr '22

19 Apr '22

Attention is currently required from: Subrata Banik, Paul Menzel, Angel Pons. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63615 ) Change subject: intel/common/../systemagent: Add sa_get_mchbar_base api ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63615/comment/703bb828_b3990c93 PS4, Line 11: enabling > enable Done https://review.coreboot.org/c/coreboot/+/63615/comment/b32a1eaf_92bb039e PS4, Line 13: > > Yes, I'd consider removing the code enabling MCHBAR in romstage. […] Implement seperate API for handle this. -- To view, visit https://review.coreboot.org/c/coreboot/+/63615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4c7af3ea8c2b2b6afcc76e1165fadbe15e0bceb Gerrit-Change-Number: 63615 Gerrit-PatchSet: 6 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 19 Apr 2022 04:35:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2022