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Change subject: mb/google/brya/var/redrix: Add alias back to RP6 WWAN device
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Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/dedede/variants/beadrix/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/63652/comment/18d9d491_8177951f
PS2, Line 139: chip drivers/i2c/sx9324
According to src/drivers/i2c/sx9324/sx9324.c, you may need to provide register uid for ACPI name _UID generation.
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Change subject: mb/google/dedede/var/beadrix: Add a Proximity Sensor SX9324 for SAR
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Patch Set 2:
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Patchset:
PS2:
hi Teddy, trivial or not, is it possible to get ECS to share power related impact thereafter?
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Change subject: soc/intel/alderlake: Configure DDR5 Physical channel width to 64
......................................................................
Patch Set 8:
(2 comments)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/52730/comment/66201811_47d9d8a4
PS8, Line 15: #define DDR5_CHANNELS CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
> I see your point, Nico. EDS vol. 1 does seem to indicates it is always effectively 128 bits wide […]
I assume original calculation will mislead the dimms calculation. https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi…https://review.coreboot.org/c/coreboot/+/52730/comment/de3b0041_a838f342
PS8, Line 15: CHANNEL_COUNT(DDR5_PHYSICAL_CH_WIDTH)
divided physical channel by 2 is more match the EDS. @Meera, could you try that work or not?
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Change subject: soc/common/smbus: Add support for reading spd data via smbus for DDR5
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/common/block/smbus/smbuslib.c:
https://review.coreboot.org/c/coreboot/+/52731/comment/35aa2e1d_c6cd81a1
PS10, Line 123: for (byte = 0; byte < stop; byte++) {
question here, does DDR5 only support byte read? or can support block read? smbus_block_read
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Change subject: mb/google/brya/var/corta: modify DQ/ DQS table
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63681/comment/6e2f2834_afa102c1
PS1, Line 7: crota: modify DQ/ DQS table
> mb/google/brya/var/corta
Done
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Change subject: mb/google/brya/var/corta: enable boot from SSD/ eMMC
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63683/comment/e326d99e_38b42ddf
PS4, Line 7: crota: enable boot from SSD/ eMMC
> mb/google/brya/var/corta
Done
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Change subject: mb/google/brya/var/corta: limit dram speed at 4800
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63682/comment/1e923406_a248a4ea
PS1, Line 7: crota: limit dram speed at 4800
> mb/google/brya/var/corta
Done
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Change subject: mb/google/brya/var/redrix: Add alias back to RP6 WWAN device
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63683
to look at the new patch set (#5).
Change subject: mb/google/brya/var/corta: enable boot from SSD/ eMMC
......................................................................
mb/google/brya/var/corta: enable boot from SSD/ eMMC
- Fix eMMC reset/ enable GPIO pins.
- Fix clk_req and clk_src
BUG=b:229437061
BRANCH=none
TEST=build and without error
Signed-off-by: Scott Chao <scott_chao(a)wistron.corp-partner.google.com>
Change-Id: Id16e292ec7557d1780516a267bd752014d98e463
---
M src/mainboard/google/brya/variants/crota/overridetree.cb
1 file changed, 6 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63683/5
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